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DM163006 Datasheet(PDF) 247 Page - Microchip Technology |
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DM163006 Datasheet(HTML) 247 Page - Microchip Technology |
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247 / 320 page ![]() 2001 Microchip Technology Inc. Advance Information DS39541A-page 247 PIC18C601/801 RETURN Return from Subroutine Syntax: [ label ] RETURN [s] Operands: s ∈ [0,1] Operation: (TOS) → PC, if s = 1 (WS) → W, (STATUSS) → STATUS, (BSRS) → BSR, PCLATU, PCLATH are unchanged Status Affected: None Encoding: 0000 0000 0001 001s Description: Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter. If ’s’ = 1, the contents of the shadow registers WS, STA- TUSS and BSRS are loaded into their corresponding registers, WREG, STATUS and BSR. If ’s’ = 0, no update of these registers occurs (default). Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation Process Data Pop PC from stack No operation No operation No operation No operation Example: RETURN After Call PC = TOS RETURN FAST Before Instruction WRG = 04h STATUS = 00h BSR = 00h After Instruction WREG = 04h STATUS = 00h BSR = 00h PC = TOS RLCF Rotate Left f through Carry Syntax: [ label ] RLCF f [,d [,a]] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f<n>) → dest<n+1>, (f<7>) → C, (C) → dest<0> Status Affected: C,N,Z Encoding: 0011 01da ffff ffff Description: The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0 the result is placed in WREG. If 'd' is 1 the result is stored back in register 'f' (default). If ’a’ is 0, the Access Bank will be selected, overriding the BSR value. If ’a’ is 1, the Bank will be selected as per the BSR value. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ’f’ Process Data Write to destination Example: RLCF REG, W Before Instruction REG = 1110 0110 C= 0 N= ? Z= ? After Instruction REG = 1110 0110 WREG = 1100 1100 C= 1 N= 1 Z= 0 C register f |
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