AT90USB646 datasheet(158/456 Pages) ATMEL

158 / 456 page

158

7593L–AVR–09/12

AT90USB64/128

Table 16-5 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to fast PWM

mode.

Note:

1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM mode” on page 151

for more details.

Table 16-6 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase cor-

rect PWM mode.

Note:

1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Phase correct PWM mode” on

page 153 for more details.

• Bits 3, 2 – Res: Reserved bits

These bits are reserved bits in the Atmel AT90USB64/128 and will always read as zero.

• Bits 1:0 – WGM21:0: Waveform Generation mode

Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting

sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-

form generation to be used, see Table 16-7. Modes of operation supported by the Timer/Counter

unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of

Pulse Width Modulation (PWM) modes (see “Modes of operation” on page 150).

Table 16-5.

Compare Output mode, fast PWM mode (1).

COM2B1

COM2B0

Description

Normal port operation, OC2B disconnected.

Reserved

Clear OC2B on Compare Match, set OC2B at TOP

Set OC2B on Compare Match, clear OC2B at TOP

Table 16-6.

Compare Output mode, phase correct PWM mode (1).

COM2B1

COM2B0

Description

Normal port operation, OC2B disconnected

Reserved

Clear OC2B on Compare Match when up-counting. Set OC2B on Compare

Match when down-counting

Set OC2B on Compare Match when up-counting. Clear OC2B on Compare

Match when down-counting

Table 16-7.

Waveform Generation mode bit description.

Mode

WGM2

WGM1

WGM0

Timer/Counter

mode of operation

TOP

Update of

OCRx at

TOV flag

set on

(1)(2)

Normal

0xFF

Immediate

MAX

PWM, phase correct

0xFF

TOP

BOTTOM

CTC

OCRA

Immediate

MAX

Fast PWM

0xFF

TOP

MAX

100

Reserved

–

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