AT90USB646 datasheet(49/456 Pages) ATMEL

49 / 456 page

7593L–AVR–09/12

AT90USB64/128

7.10

PLL

The PLL is used to generate internal high frequency (48MHz) clock for USB interface, the PLL

input is generated from an external low-frequency (the crystal oscillator or external clock input

pin from XTAL1). The internal RC oscillator can not be used for USB operations.

7.10.1

Internal PLL for USB interface

The internal PLL in Atmel AT90USB64/128 generates a clock frequency that is 24× multiplied

from nominally 2MHz input. The source of the 2MHz PLL input clock is the output of the internal

PLL clock prescaler that generates the 2MHz (see Section 7.10.2 for PLL interface).

Figure 7-4.

PLL clocking system.

7.10.2

PLLCSR – PLL Control and Status Register

• Bit 7..5 – Res: Reserved bits

These bits are reserved bits in the AT90USB64/128 and always read as zero.

• Bit 4..2 – PLLP2:0 PLL prescaler

These bits allow to configure the PLL input prescaler to generate the 2MHz input clock for the

PLL.

Reserved

CLKPS3

CLKPS2

CLKPS1

CLKPS0

Clock division factor

8MHz

RC OSCILLATOR

XTAL1

XTAL2

OSCILLATORS

PLL

24x

PLLE

Lock

detector

PLOCK

clkUSB

System clock

clk

2MHz

PLL clock

prescaler

(48MHz)

Bit

5432

$29 ($29)

PLLP2

PLLP1

PLLP0

PLLE

PLOCK

PLLCSR

Read/write

R/W

Initial value

0000

0/1

AT90USB646 Datasheet(PDF) 49 Page - ATMEL Corporation

AT90USB646 Datasheet(HTML) 49 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL