PCF8536AT datasheet(46/74 Pages) NXP

46 / 74 page

PCF8536

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Product data sheet

Rev. 2 — 21 February 2012

46 of 74

NXP Semiconductors

PCF8536

Universal LCD low multiplex driver with 6 channel PWM generator

Bus interfaces

9.1 Control byte and register selection

After initiating the communication over the bus and sending the slave address (I2C-bus,

see Section 9.2) or subaddress (SPI-bus, see Section 9.3), a control byte follows. The

purpose of this byte is to indicate both, the content for the following data bytes (RAM,

command, or PWM data) and to indicate that more control bytes will follow.

Typical sequences could be:

• Slave address/subaddress - control byte - command byte - command byte - command

byte - end

• Slave address/subaddress - control byte - RAM byte - RAM byte - RAM byte - end

• Slave address/subaddress - control byte - command byte - control byte - RAM byte -

end

In this way, it is possible to send a mixture of RAM, PWM and command data in one

access or alternatively, to send just one type of data in one access.

9.2 I2C-bus interface

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor when connected to the output

stages of a device. Data transfer may be initiated only when the bus is not busy.

Table 36.

Control byte description

Bit

Symbol

Value

Description

7CO

continue bit

last control byte

control bytes continue

6 to 5

RS[1:0]

command register

RAM data

PWM data

unused

4 to 0

unused

Fig 31. Control byte format

013aaa461

not relevant

RS[1:0]

MSB

LSB

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