PCF8536AT datasheet(47/74 Pages) NXP

47 / 74 page

PCF8536

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 21 February 2012

47 of 74

NXP Semiconductors

PCF8536

Universal LCD low multiplex driver with 6 channel PWM generator

9.2.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as a control signal (see Figure 32).

9.2.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy.

A HIGH-to-LOW change of the data line, while the clock is HIGH, is defined as the START

condition (S).

A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP

condition (P).

The START and STOP conditions are shown in Figure 33.

9.2.3 System configuration

A device generating a message is a transmitter, a device receiving a message is the

receiver. The device that controls the message is the master and the devices which are

controlled by the master are the slaves. The system configuration is shown in Figure 34.

Fig 32. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 33. Definition of START and STOP conditions

mbc622

SDA

SCL

STOP condition

SDA

SCL

START condition

Fig 34. System configuration

mga807

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

SLAVE

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

PCF8536AT Datasheet(PDF) 47 Page - NXP Semiconductors

PCF8536AT Datasheet(HTML) 47 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74

Datasheet Download

Link URL