PCF8536AT datasheet(16/74 Pages) NXP

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PCF8536

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Product data sheet

Rev. 2 — 21 February 2012

16 of 74

NXP Semiconductors

PCF8536

Universal LCD low multiplex driver with 6 channel PWM generator

[1]

Default value.

8.1.7 Command: set-MUX-mode

The multiplex drive mode is configured with the bits described in Table 18.

[1]

Default value.

8.1.8 Command: set-bias-mode

The set-bias-mode command allows setting the bias level.

[1]

Default value.

8.1.9 Command: frame-frequency-LCD

With the frame-frequency-LCD command, the frame frequency for the display can be

configured. The clock frequency determines the frame frequency.

The system is designed for a 230 kHz clock. It is either internally generated or externally

provided. Alternatively a 9.6 kHz clock signal can be provided as well. The EFR bit (see

Table 10) has to be set according to the external clock frequency.

When EFR is set to 9.6 kHz, then the LCD frame frequency is calculated with Equation 1:

(1)

Table 17.

GPMO mode definition

GPM0[1:0] to GPM5[1:0]

Mode

Description

00[1], 01

LCD

output is an LCD segment

static

output is static GPO

PWM

output is PWM GPO

Table 18.

Set-MUX-mode - set multiplex drive mode command bit description

Bit

Symbol

Value

Description

7 to 2

000000

fixed value

1 to 0

M[1:0]

00[1], 01

1:8 multiplex drive mode; eight backplanes

1:6 multiplex drive mode; 6 backplanes

1:4 multiplex drive mode; 4 backplanes

Table 19.

Set-bias-mode - set bias mode command bit description

Bit

Symbol

Value

Description

7 to 2

000001

fixed value

1 to 0

B[1:0]

00[1]. 01

1⁄4 bias

1⁄3 bias

1⁄2 bias

Table 20.

Frame-frequency-LCD - frame frequency and output clock frequency command

bit description

Bit

Symbol

Value

Description

7 to 5

001

fixed value

4 to 0

FD[4:0]

see Table 21

frequency prescaler

fr LCD



clk ext



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