AD9887APCB datasheet(35/52 Pages) AD

35 / 52 page

AD9887A

Rev. B | Page 35 of 52

Address

Read and

Write, or

Read Only

Bits

Default

Value

Description

0x22

R/W

7:0

00000000

Must be set to default.

0x23

R/W

7:0

00000000

Must be set to 0x2A for proper operation.

0x24

R/W

7:0

00000000

Must be set to default.

0x25

R/W

7:0

11110000

Must be set to default.

0x26

R/W

7:0

11111111

Must be set to default.

0x27

00001111

Must be set to default

1 The AD9887A only updates the PLL divide ratio when the LSBs are written to Register 0x02.

2-WIRE SERIAL CONTROL REGISTER DETAILS

Chip Identification

0x00 7:0

Chip Revision

Bit 7 through Bit 4 represent functional revisions to the

analog interface. Changes in these bits generally indicate

that software and/or hardware changes are required for

the chip to work properly. Bit 3 through Bit 0 represent

nonfunctional related revisions and are reset to 0000

when the MSBs are changed. Changes in these bits are

considered transparent to the user.

PLL Divider Control

0x01 7:0

PLL Divide Ratio MSBs

The 8 MSBs of the 12-bit PLL divide ratio PLLDIV. (The

operational divide ratio is PLLDIV + 1.)

The PLL derives a pixel clock from the incoming Hsync

signal. The pixel clock frequency is then divided by an

integer value, such that the output is phase-locked to

Hsync. This PLLDIV value determines the number of

pixel times (pixels plus horizontal blanking overhead)

per line. This is typically 20% to 30% more than the

number of active pixels in the display.

The 12-bit value of the PLL divider supports divide ratios

from 221 to 4095. The higher the value loaded in this

respect to a fixed Hsync frequency. VESA has established

standard timing specifications that help determine the value

for PLLDIV as a function of horizontal and vertical display

resolution and frame rate (Table 7). However, many com-

puter systems do not conform precisely to the recom-

mendations, and these numbers should be used only as a

guide. The display system manufacturer should provide

automatic or manual means for optimizing PLLDIV. An

incorrectly set PLLDIV usually produces one or more

vertical noise bars on the display. The greater the error, the

greater the number of bars produced. The power-up default

of PLLDIV is 1693 (PLLDIVM = 0x69, PLLDIVL = 0xDx).

The AD9887A updates the full divide ratio only when

the LSBs are changed. Writing to this register by itself

does not trigger an update.

0x02 7:4

PLL Divide Ratio LSBs

The 4 LSBs of the 12-bit PLL divide ratio PLLDIV. The

operational divide ratio is PLLDIV + 1.

The power-up default value of PLLDIV is 1693

(PLLDIVM = 0x69, PLLDIVL = 0xDx).

The AD9887A updates the full divide ratio only when

the user writes to this register.

Clock Generator Controls

0x03 7

Test

Must be set to 1 for proper device operation.

0x03 6:5

VCO Range Select

Two bits that establish the operating range of the clock

generator.

VCORNGE must be set to correspond with the desired

operating frequency (incoming pixel rate).

The PLL provides the best jitter performance at high

frequencies. To output low pixel rates while minimizing

jitter, the PLL operates at a higher frequency and divides

down the clock rate afterwards. Table 10 shows the pixel

rates for each VCO range setting. The PLL output divisor

is automatically selected with the VCO range setting.

Table 10. VCO Ranges

VCORNGE

Pixel Rate Range

12 to 37

37 to 74

74 to 140

140 to 170

The power-up default value is 01.

AD9887APCB Datasheet(PDF) 35 Page - Analog Devices

AD9887APCB Datasheet(HTML) 35 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL