AD9887APCB datasheet(39/52 Pages) AD

39 / 52 page

AD9887A

Rev. B | Page 39 of 52

0x0F 1

Green Clamp Select

A bit that determines whether the green channel is

clamped to ground or to midscale.

Table 23. Green Clamp Select Settings

Clamp

Function

Clamp to ground

Clamp to midscale (Pin 109)

The default setting for this register is 0.

0x0F 0

Blue Clamp Select

A bit that determines whether the blue channel is

clamped to ground or to midscale.

Table 24. Blue Clamp Select Settings

Clamp

Function

Clamp to ground

Clamp to midscale (Pin 99)

The default setting for this register is 0.

Mode Control 2

0x10 7

Data Output Clock Invert (CKINV)

A control bit for the inversion of the output data clocks

(Pin 134 and Pin 135). This function only works for the

digital interface. When not inverted, data is output upon

the trailing edge of the data clock. See Figure 37 through

Figure 40 for how this affects timing.

Table 25. Data Output Clock Invert (CKINV) Settings

CKINV

Function

Not inverted

Inverted

The default for this register is 0.

0x10 6

Pixel Select

This bit selects either one or two pixels per clock mode

for the digital interface. It determines whether the

output is from a single port (even port only) at the full

data rate, or from two ports (both even and odd ports) at

half the full data rate per port. Logic 0 selects one pixel

per clock (even port only). Logic 1 selects two pixels per

clock (both ports). See the Digital Interface Timing

Diagrams (Figure 37 through Figure 40) for visual

representations of this function. Note that this function

operates exactly like the demux function on the analog

interface.

Table 26. Pixel Select Settings

Pixel Select

Function

One pixel per clock

Two pixels per clock

The default for this register is 0.

0x10 5, 4

Output Drive

These two bits select the drive strength for the high

speed digital outputs (all data output and clock output

pins). Higher drive strength results in faster rise/fall

times and enables easier capture of data in general.

Lower drive strength results in slower rise/fall times and

reduces EMI and digitally generated power supply noise.

The exact timing specifications for each of these modes

are specified in Table 7.

Table 27. Output Drive Strength Settings

Bit 5

Bit 4

Result

High drive strength

Medium drive strength

Low drive strength

The default for this register is 11. This option works on

both the analog and digital interfaces.

0x10 3

Power-Down Outputs (PDO)

This bit can put the outputs into a high impedance mode.

This applies to all outputs except SOGOUT and REFOUT.

Table 28. Power-Down Output (PDO) Settings

PDO

Function

Normal operation

Three-state

The default for this register is 0. This option works on

both the analog and digital interfaces.

0x10 2

Sync Detect Polarity

This pin controls the polarity of the sync detect output

pin (Pin 136).

Table 29. Sync Detect Polarity Settings

Polarity

Function

Activity = Logic 1 output

Activity = Logic 0 output

The default for this register is 0. This option works on

both the analog and digital interfaces.

AD9887APCB Datasheet(PDF) 39 Page - Analog Devices

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