AD9887APCB datasheet(19/52 Pages) AD

19 / 52 page

AD9887A

Rev. B | Page 19 of 52

ADC

DAC

OFFSET

REF

x1.2

CLAMP

VOFF

GAIN

Figure 5. ADC Block Diagram (Single-Channel Output)

GAIN

0xFF

0x00

1.0

0.5

OFFSET = 0x00

OFFSET = 0x3F

OFFSET = 0x7F

OFFSET = 0x00

OFFSET = 0x7F

OFFSET = 0x3F

Figure 6. Gain and Offset Control

VOFF

(128 CODES)

0.5V

VOFF

(128 CODES)

Figure 7. Relationship of Offset Range to Input Range

SYNC-ON-GREEN INPUT

The sync-on-green input operates in two steps. First, with the

aid of a negative peak detector, it sets a baseline clamp level

from the incoming video signal. Second, it sets the sync trigger

level (nominally 150 mV above the negative peak). The exact

trigger level is variable and can be programmed via Register 0x11.

The sync-on-green input must be ac-coupled to the green analog

input through its own capacitor, as shown in Figure 8.

The value of the capacitor must be 1 nF ± 20%. If sync-on-green

is not used, this connection is not required and SOGIN should

be left unconnected. (Note that the sync-on-green signal is always

negative polarity.) See the Theory of Operation—Sync Processing

section for more information.

GAIN

SOGIN

1nF

RAIN

47nF

BAIN

47nF

Figure 8. Typical Clamp Configuration for RGB and YUV Applications

CLOCK GENERATION

A phase-locked loop (PLL) is used to generate the pixel clock.

The HSYNC input provides a reference frequency for the PLL.

A voltage-controlled oscillator (VCO) generates a much higher

pixel clock frequency. This is divided by the PLL divide value

(MSBs in Register 0x01 and LSBs in Register 0x02) and phase

compared with the HSYNC input. Any error is used to shift the

VCO frequency and maintain lock between the two signals.

The stability of this clock is important for providing the clearest,

most stable image. During each pixel time, there is a period when

the signal slews from the old pixel amplitude and settles at its

new value. Then, the input voltage is stable until the signal slews

to a new value (see Figure 9). The ratio of the slewing time to the

stable time is a function of the bandwidth of the graphics DAC,

the bandwidth of the transmission system (cable and termination),

and the overall pixel rate. Clearly, if the dynamic characteristics

of the system remain fixed, the slewing and settling times are

likewise fixed. Subtract these times from the total pixel period to

determine the stable period. At higher pixel frequencies, both the

total cycle time and stable pixel time are shorter.

PIXEL CLOCK

INVALID SAMPLE TIMES

Figure 9. Pixel Sampling Times

AD9887APCB Datasheet(PDF) 19 Page - Analog Devices

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