AD9887APCB datasheet(43/52 Pages) AD

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AD9887A

Rev. B | Page 43 of 52

0x17 7:0

Precoast

This register allows the coast signal to be applied prior to

the Vsync signal. This is necessary in cases where pre-

equalization pulses are present. This register defines the

number of edges that are filtered before Vsync on a

composite sync.

The default is 0.

0x18 7:0

Postcoast

This register allows the coast signal to be applied

following the Vsync signal. This is necessary when

postequalization pulses are present. This register defines

the number of edges that are filtered after Vsync on a

composite sync.

The default is 0.

0x19 7:0

Test

Must be set to default.

0x1A 7:0

Test

Must be set to 0x41 for proper operation.

0x1B 7:0

Test

Must be set to 0x00 for autogain mode and 0x10 for

manual-gain mode.

0x1C 7:3

Test

Must be set to 00000*** for autogain mode and 00101***

for manual-gain mode.

0x1C 2

CbCr Output Order

In 4:2:2 mode, the red and blue channels can be

interchanged to help satisfy board layout or timing

requirements, but the green channel must be configured

for Y. Register 0x1C, Bit 2, controls the order that the

U/V (CbCr) data is output. If this bit is high, the red

channel data precedes the blue channel data. If this bit is

low, the blue channel data precedes the red channel data.

See the example in Table 51.

Table 51. 4:2:2 Input/Output Configuration

Channel

Input

Connection

Output Format

Red

V/U if 0x1C Bit 2 = 1;

U/V if 0x1C Bit 2 = 0

Green

Blue

High impedance

0x1C 1

Test Bits

Must be set to 0 for standard input sampling.

0x1C 0

4:2:2 Output Mode Select

4:2:2 mode can be used to reduce the number of data

lines used from 24 to 16 for applications using YUV,

YCbCr, or YPbPr graphics signals. See Figure 27 for a

timing diagram for this mode.

Table 52. 4:2:2 Output Mode Select

Select

Output Mode

4:4:4

4:2:2

0x1D 6

HDCP Keys Detected

This bit indicates the presence of HDCP keys read from

the external EEPROM.

Table 53. HDCP Key Status

Select

HDCP Key Status

HDCP keys present

HDCP keys not present

0x1E 7:0

Test Register

Must be set to 0xFF for proper operation.

0x1F 7:0

Test Register

Must be set to 0x84 for proper operation.

0x20 7

HDCP A0 Serial Address Bit

This bit sets the value of the A0 bit for the DDC

serial port.

Table 54. HDCP A0 Serial Address

Select

Serial Address

A0 bit = 1, address = 0x76

A0 bit = 0, address = 0x74

The default setting is 0.

0x20 6

MDA Pin Select

This bit sets the function of Pin 49 to MDA when set at 1.

Table 55. MDA Pin Select

Select

Output Mode

Pin 49 = MDA for HDCP

Pin 49 = CTL3 signal

The default setting is 0.

0x20 5

Analog Input Bandwidth Control

This bit controls the analog input bandwidth.

Table 56. Analog Input Bandwidth Control

Select

Input Bandwidth

High analog input bandwidth

Low analog input bandwidth

The default setting 0.

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