APW7165C datasheet(14/20 Pages) ANPEC

14 / 20 page

Rev. A.2 - Oct., 2012

APW7165C

www.anpec.com.tw

Application Information (Cont.)

Compensation (Cont.)

Figure 6. Converter Gain & Frequency

MOSFET Selection

The selection of the N-channel power MOSFETs is deter-

mined by the R

DS(ON), reverse transfer capacitance (CRSS),

and maximum output current requirement.The losses in

the MOSFETs have two components: conduction loss and

transition loss. For the upper and lower MOSFET, the

losses are approximately given by the following equations:

UPPER = IOUT

2 (1+ TC)(R

DS(ON))D + (0.5)(Iout)(VIN)(tsw)FSW

LOWER = IOUT

2 (1+ TC)(R

DS(ON))(1-D)

where I

OUT is the load current

TC is the temperature dependency of R

DS(ON)

SW is the switching frequency

sw is the switching interval

D is the duty cycle

Note that both MOSFETs have conduction losses while

the upper MOSFET includes an additional transition loss.

The switching internal, t

sw, is the function of the reverse

transfer capacitance C

RSS. Figure 7 illustrates the switch-

ing waveform internal of the MOSFET.

The (1+TC) term factors in the temperature dependency

of the R

DS(ON) and can be extracted from the “RDS(ON) vs Tem-

perature”curve of the power MOSFET.

−

Layout Consideration

In any high switching frequency converter, a correct lay-

out is important to ensure proper operation of the

regulator. With power devices switching at 300kHz,the

resulting current transient will cause voltage spike across

the interconnecting impedance and parasitic circuit

elements. As an example, consider the turn-off transition

of the PWM MOSFET. Before turn-off, the MOSFET is car-

rying the full load current. During turn-off, current stops

flowing in the MOSFET and is free-wheeling by the lower

MOSFET and parasitic diode. Any parasitic inductance of

the circuit generates a large voltage spike during the

switching interval. In general, using short and wide printed

circuit traces should minimize interconnecting imped-

Figure 7. Switching waveform across MOSFET

2. Place the zero F

Z before the LC filter double poles FLC:

Z = 0.75 x FLC

Calculate the C1 by the equation:

3. Set the pole at the half the switching frequency:

P = 0.5xFSW

Calculate the C2 by the equation:

0.75

ESR

P=0.5FSW

Z=0.75FLC

Frequency

PWM &

Filter Gain

Compensation

Gain

Converter

Gain

20 . log(gm . R3)

∆V

OSC

20.log

Time

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