APW7165C datasheet(15/20 Pages) ANPEC

15 / 20 page

Rev. A.2 - Oct., 2012

APW7165C

www.anpec.com.tw

Application Information (Cont.)

Layout Consideration (Cont.)

Figure 8. Layout Guidelines

- Keep the switching nodes (UGATE, LGATE, and PHASE)

away from sensitive small signal nodes since these

nodes are fast moving signals. Therefore, keep traces

to these nodes as short as possible.

- The traces from the gate drivers to the MOSFETs (UG

and LG) should be short and wide.

- Place the source of the high-side MOSFET and the drain

of the low-side MOSFET as close as possible. Minimiz-

ing the impedance with wide layout plane between the

two pads reduces the voltage bounce of the node.

- Decoupling capacitor, compensation component, the

resistor dividers, and boot capacitors should be close

their pins. (For example, place the decoupling ceramic

capacitor near the drain of the high-side MOSFET as

close as possible. The bulk capacitors are also placed

near the drain).

- The input capacitor should be near the drain of the up-

per MOSFET; the output capacitor should be near the

loads. The input capacitor GND should be close to the

output capacitor GND and the lower MOSFET GND.

- The drain of the MOSFETs (V

IN and PHASE nodes) should

be a large plane for heat sinking.

- The R

OCSET resistance should be placed near the IC as

close as possible.

ances and the magnitude of voltage spike. And signal

and power grounds are to be kept separate till combined

using ground plane construction or single point

grounding. Figure 8. illustrates the layout, with bold lines

indicating high current paths; these traces must be short

and wide. Components along the bold lines should be

placed lose together. Below is a checklist for your layout:

VCC

BOOT

PHASE

UGATE

LGATE

OUT

APW7165C

OCSET

Close to IC

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