APW7199 datasheet(18/24 Pages) ANPEC

18 / 24 page

Rev. A.4 - Oct., 2010

APW7199

www.anpec.com.tw

Application Information (Cont.)

Output Capacitor Selection (Cont.)

Input Capacitor Selection

The input capacitor is chosen based on the voltage rating

and the RMS current rating. For reliable operation, select-

ing the capacitor voltage rating to be at least 1.3 times

higher than the maximum input voltage. The maximum

RMS current rating requirement is approximately I

OUT/2,

where I

OUT is the load current. During power-up, the input

capacitors have to handle great amount of surge current.

For low-duty notebook appliactions, ceramic capacitor is

recommended. The capacitors must be connected be-

tween the drain of high-side MOSFET and the source of

low-side MOSFET with very low-impeadance PCB layout.

MOSFET Selection

The selection of the N-channel power MOSFETs are

determined by the R

DS(ON), reversing transf er c ap ac i -

tance (C

RSS) and maximum output current requirement.

The losses in the MOSFETs have two components:

conduction loss and transition loss. For the high-side

and low-side MOSFETs, the losses are approximately

given by the following equations:

high-side = IOUT

2(1+ TC)(R

DS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW

low-side = IOUT

2(1+ TC)(R

DS(ON))(1-D)

Layout Consideration

During turn-off, current stops flowing in the MOSFET and

is freewheeling by the low side MOSFET and parasitic

diode. Any parasitic inductance of the circuit generates a

large voltage spike during the switching interval. In

general, using short and wide printed circuit traces should

minimize interconnecting impedances and the magni-

tude of voltage spike. Besides, signal and power grounds

are to be kept separating and finally combined using

ground plane construction or single point grounding. Fig-

ure 3 illustrates the layout, with bold lines indicating high

current paths; these traces must be short and wide. Com-

ponents along the bold lines should be placed lose

together. Below is a checklist for your layout:

Where

OUT is the load current

TC is the temperature dependency of R

DS(ON)

SW is the switching frequency

SW is the switching interval

D is the duty cycle

Note that both MOSFETs have conduction losses while

the high-side MOSFET includes an additional transition

loss. The switching interval, t

SW, is the function of the re-

verse transfer capacitance C

RSS. The (1+TC) term is a

factor in the temperature dependency of the R

DS(ON) and

can be extracted from the “R

DS(ON) vs. Temperature” curve

of the power MOSFET.

= Keep the switching nodes (UGATE, LGATE/OCSET,

BOOT, and PHASE) away from sensitive small signal

nodes since these nodes are fast moving signals.

Therefore, keep traces to these nodes as short as pos-

sible and there should be no other weak signal traces in

parallel with theses traces on any layer.

= The signals going through theses traces have both

high dv/dt and high di/dt with high peak charging and dis-

charging current. The traces from the gate drivers to the

MOSFETs (UGATE and LGATE/OCSET) should short and

wide.

= Place the source of the high-side MOSFET and the

drain of the low-side MOSFET as close as possible. Mini-

mizing the impedance with wide layout plane between

the two pads reduces the voltage bounce of the node. In

addition, the large layout plane between the drain of the

MOSFETs (V

IN and PHASE nodes) can get better heat

sinking.

In any high switching frequency converter, a correct lay-

out is important to ensure proper operation of the

regulator. With power devices switching at higher

frequency, the resulting current transient will cause volt-

age spike across the interconnecting impedance and

parasitic circuit elements. As an example, consider the

turn-off transition of the PWM MOSFET. Before turn-off

condition, the MOSFET is carrying the full load current.

= Decoupling capacitors, the resistor-divider, and boot

capacitor should be close to their pins. (For example, place

the decoupling ceramic capacitor close to the drain of the

high-side MOSFET as close as possible.)

the voltage excursion during load step change. Another

aspect of the capacitor selection is that the total AC cur-

rent going through the capacitors has to be less than the

rated RMS current specified on the capacitors in order to

prevent the capacitor from over-heating.

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