AD5663 datasheet(21/32 Pages) AD

21 / 32 page

Data Sheet

AD5623R/AD5643R/AD5663R

Rev. F | Page 21 of 32

At this stage, the SYNC line can be kept low or be brought high.

In either case, it must be brought high for a minimum of 15 ns

before the next write sequence, so that a falling edge of SYNC

can initiate the next write sequence.

Because the SYNC buffer draws more current when VIN = 2 V

than it does when VIN = 0.8 V, SYNC should be idled low between

write sequences for even lower power operation. As mentioned

previously, it must, however, be brought high again just before

the next write sequence.

INPUT SHIFT REGISTER

The input shift register is 24 bits wide (see Figure 52). The first

two bits are don’t cares. The next three are Command Bit C2 to

Command Bit C0 (see Table 8), followed by the 3-bit DAC

Address A2 to DAC Address A0 (see Table 9), and, finally, the

16-, 14-, and 12-bit data-word.

The data-word comprises the 16-, 14-, and 12-bit input codes,

followed by zero, two, or four don’t care bits, for the AD5663R,

AD5643R, and AD5623R, respectively (see Figure 51, Figure 52,

and Figure 53). The data bits are transferred to the DAC register

on the 24th falling edge of SCLK.

Table 8. Command Definition

Command

Write to Input Register n

Update DAC Register n

Write to Input Register n, update all

(software LDAC)

Write to and update DAC Channel n

Power down DAC (power up)

Reset

LDAC register setup

Internal reference setup (on/off )

Table 9. Address Command

ADDRESS (n)

DAC A

DAC B

Reserved

All DACs

SYNC INTERRUPT

In a normal write sequence, the SYNC line is kept low for at

least 24 falling edges of SCLK, and the DAC is updated on the

24th falling edge. However, if SYNC is brought high before the

24th falling edge, this acts as an interrupt to the write sequence.

The shift register is reset, and the write sequence is seen as

invalid. Neither an update of the DAC register contents nor a

change in the operating mode occurs (see Figure 54).

D15

D14

D13

D12

D11

D10

DB23 (MSB)

DB0 (LSB)

COMMAND BITS

ADDRESS BITS

DATA BITS

Figure 51. AD5663R Input Shift Register Contents

D11

D10

D13

D12

DB23 (MSB)

DB0 (LSB)

COMMAND BITS

ADDRESS BITS

DATA BITS

Figure 52. AD5643R Input Shift Register Contents

XXX

D11

D10

DB23 (MSB)

DB0 (LSB)

COMMAND BITS

ADDRESS BITS

DATA BITS

Figure 53. AD5623R Input Shift Register Contents

DIN

DB23

DB0

VALID WRITE SEQUENCE, OUTPUT UPDATES

ON THE 24TH FALLING EDGE

SYNC

SCLK

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 24TH FALLING EDGE

Figure 54. SYNC Interrupt Facility

AD5663 Datasheet(PDF) 21 Page - Analog Devices

AD5663 Datasheet(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL