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ADF4112BCP Datasheet(PDF) 24 Page - Analog Devices

Part # ADF4112BCP
Description  50 MHz to 1000 MHz Quadrature Demodulator
PDF  28 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADF4112BCP Datasheet(HTML) 24 Page - Analog Devices

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AD8348
Rev. A | Page 24 of 28
differential impedance of 200 Ω (100 Ω per side). The
differential inputs should then be fed into SMA connectors
MXIP and MXIN.
Mixer Outputs
The I and Q mixer outputs are available through the IMXO and
QMXO SMA connectors. These outputs are biased to VCMO
and are not designed to drive loads smaller than 200 Ω. To
prevent damage to test equipment that cannot tolerate dc biases,
pads for series dc-blocking capacitors are provided. These pads
are populated with 0 Ω by default.
Baseband Outputs
The baseband outputs are made available at the IOPP, IOPN,
QOPP, and QOPN test points and SMA connectors. These
outputs are not designed to be connected directly to 50 Ω loads
and should be presented with loads of approximately 2 kΩ or
greater.
The dc bias level of the baseband amplifier outputs are by
default tied to VREF through LK11. If desired, the dc bias level
can be changed by removing LK11 and driving a dc voltage
onto the VCMO test point.
L3I
OPEN
L2I
OPEN
L1I
OPEN
R2I
OPEN
R1I
OPEN
C7I
OPEN
C6I
OPEN
C5I
OPEN
C4I
OPEN
C3I
OPEN
C2I
OPEN
C1I
OPEN
LK2I
VCMO
J1I
IMXO
C13
0.1µF
LK1I
VCMO
LK11
LK4I
LK3I
C10I
0Ω
C32
1000pF
C31
1000pF
R31
57.6Ω
1
3
5
4
J21
LO
C21
1000pF
C22
1000pF
R21
60.4Ω
+VS
C51
100pF
C52
0.1µF
+VS
C53
100pF
C54
0.1µF
+VS
MXIN
MXIP
R42
0Ω
R44
OPEN
R43
OPEN
C42
1000pF
C43
1000pF
SW13
C12
0.1µF
R13
OPEN
J3I
IOPN
J2I
IOPP
R5I
0Ω
R4I
0Ω
IOPN
IOPP
GND
C9I
OPEN
C8I
OPEN
C0I
0.1µF
C0Q
0.1µF
C11
4.7µF
IFIP
EXT
POT
R14
10kΩ
LK5I
LK5Q
+VS
IOFS
QOFS
ENBL
VENB
R3I
49.9Ω
R12
10kΩ
R11
49.9Ω
ENBL
DENBL
SW11
VREF
R32
174Ω
T21
ETC1-1-13
AD8348
IMXO
L3Q
OPEN
L2Q
OPEN
L1Q
OPEN
R2Q
OPEN
R1Q
OPEN
C7Q
OPEN
C6Q
OPEN
C5Q
OPEN
C4Q
OPEN
C3Q
OPEN
C2Q
OPEN
C1Q
OPEN
LK2Q
VCMO
VCMO
J1Q
QMXO
LK1Q
LK4Q
LK3Q
C10Q
0Ω
R3Q
49.9Ω
QMXO
SW12
J3Q
QOPN
J2Q
QOPP
R5Q
0Ω
R4Q
0Ω
QOPN
QOPP
GND
GND
C9Q
OPEN
C8Q
OPEN
+VS
IF
MX
C55
100pF
C55
0.1µF
R41
OPEN
VGIN
R15
10kΩ
POT
T41
ETK4-2T
C41
1µF
IFIP
MXIP
VPOS2 VGIN
IOFS
QOFS
VREF
ENBL
LOIN
LOIP
VPOS1 COM1
IOPN
QOPN
IOPP
QOPP
VCMO ENVG
IAIN
QAIN
COM3 COM3
IMXO
QMXO
COM2 VPOS3
IFIN
MXIN
18
17
16
15
28
27
26
25
24
23
22
21
20
19
11
12
13
14
1
2
3
4
5
6
7
8
9
10
Figure 60. Evaluation Board Schematic



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