TAS5706APAP datasheet(28/71 Pages) TI1

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Right-Justified

SCLK

32Clks

LRCLK

LeftChannel

24-BitMode

20-BitMode

16-BitMode

MSB

LSB

SCLK

32Clks

RightChannel

2-ChannelRight-Justified(SonyFormat)StereoInput

T0034-03

MSB

LSB

TAS5706A

TAS5706B

SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com

Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when

it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at

32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for

24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before

LRCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock. The DAP masks

unused leading data bit positions.

Figure 36. Right Justified 64-fS Format

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Product Folder Link(s): TAS5706A TAS5706B

TAS5706A is Not Recommended for New Designs

TAS5706APAP Datasheet(PDF) 28 Page - Texas Instruments

TAS5706APAP Datasheet(HTML) 28 Page - Texas Instruments

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