DMVA4 datasheet(5/287 Pages) TI1

5 / 287 page

System Interconnect

Serial Interfaces

Program/Data Storage

Connectivity

ARM Subsystem

32 KB

D-Cache

256 KB L2 Cache

with ECC

NEON

FPU

Cortex -A8

CPU

ICE Crusher

RAM

64 KB

Boot ROM

48 KB

32 KB

I-Cache

Imaging

Subsystem

Resizer

Parallel Cam Input

Video Processing

Subsystem

Video Capture

Display Processing

HD OSD

SD OSD

HD VENC

SD VENC

HDMI Xmt

SD DAC

HD DAC (3)

MDIO

PCIe 2.0

(One x1

Port)

EMAC

(R)(G)MII

(2)

USB 2.0

Ctrl/PHY

(2)

GPMC

ELM

MMC/SD/

SDIO

(3)

SATA

3 Gbp/s

(1 Drive)

DDR2/3

32-bit

McASP

(2)

SPI (4)

DCAN (2)

UART (3)

I C (4)

System Control

Real-Time

Clock

PRCM

GP Timer (8)

JTAG

Watchdog

Timer

Mailbox

Spinlock

CSI2 Serial Input

IPIPE

H3A

Peripherals

Miscellaneous

GPIO (4)

DMVA3, DMVA4

www.ti.com

SPRS872B – MAY 2013 – REVISED DECEMBER 2013

1.4

Functional Block Diagram

Figure 1-1 shows the functional block diagram of the device.

Figure 1-1. Functional Block Diagram

High-Performance System-on-Chip (SoC)

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