APA300 datasheet(13/178 Pages) ACTEL

13 / 178 page

ProASICPLUS Flash Family FPGAs

v5.9

2-3

Clock Resources

The ProASICPLUS family offers powerful and flexible

control of circuit timing through the use of analog

circuitry. Each chip has two clock conditioning blocks

containing a phase-locked loop (PLL) core, delay lines,

phase shifter (0

° and 180°), clock multiplier/dividers, and

all

the

circuitry

needed

for

the

selection

and

interconnection of inputs to the global network (thus

providing bidirectional access to the PLL). This permits

the PLL block to drive inputs and/or outputs via the two

global lines on each side of the chip (four total lines).

This circuitry is discussed in more detail in the

"ProASICPLUS Clock Management System" section on

page 2-10.

Clock Trees

One of the main architectural benefits of ProASICPLUS is

the set of power- and delay-friendly global networks.

ProASICPLUS offers four global trees. Each of these trees

is based on a network of spines and ribs that reach all

the tiles in their regions (Figure 2-4 on page 2-4). This

flexible clock tree architecture allows users to map up to

88 different internal/external clocks in an APA1000

device. Details on the clock spines and various numbers

of the family are given in Table 2-1 on page 2-4.

The flexible use of the ProASICPLUS clock spine allows the

designer to cope with several design requirements. Users

implementing clock-resource intensive applications can

easily route external or gated internal clocks using global

routing spines. Users can also drastically reduce delay

penalties and save buffering resources by mapping

critical high fanout nets to spines. For design hints on

using these features, refer to Actel’s Efficient Use of

ProASIC Clock Trees application note.

Figure 2-3 • High-Speed, Very Long-Line Resources

PAD RING

High-Speed Very Long-Line Resouces

SRAM

APA300 Datasheet(PDF) 13 Page - Actel Corporation

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