APA300 datasheet(23/178 Pages) ACTEL

23 / 178 page

ProASICPLUS Flash Family FPGAs

v5.9

2-13

Lock Signal

An active high Lock signal (added via the SmartGen PLL

development tool) indicates that the PLL has locked to

the incoming clock signal. The PLL will acquire and

maintain a lock even when there is jitter on the incoming

clock signal. The PLL will maintain lock with an input

jitter up to 5% of the input period, with a maximum of

5 ns. Users can employ the Lock signal as a soft reset of

the logic driven by GLB and/or GLA. Note if FIN is not

within specified frequencies, then both the FOUT and lock

signal are indeterminate.

PLL Configuration Options

The PLL can be configured during design (via flash-

configuration bits set in the programming bitstream) or

dynamically during device operation, thus eliminating

the need to reprogram the device. The dynamic

configuration bits are loaded into a serial-in/parallel-out

shift register provided in the clock conditioning circuit.

The shift register can be accessed either from user logic

within the device or via the JTAG port. Another option is

internal

dynamic

configuration

via

user-designed

hardware. Refer to Actel's ProASICPLUS PLL Dynamic

Reconfiguration Using JTAG application note for more

information.

For information on the clock conditioning circuit, refer

to Actel’s Using ProASICPLUS Clock Conditioning Circuits

application note.

Sample Implementations

Frequency Synthesis

Figure 2-13 on page 2-14 illustrates an example where

the PLL is used to multiply a 33 MHz external clock up to

133 MHz. Figure 2-14 on page 2-14 uses two dividers to

synthesize a 50 MHz output clock from a 40 MHz input

reference clock. The input frequency of 40 MHz is

multiplied by five and divided by four, giving an output

clock (GLB) frequency of 50 MHz. When dividers are

used, a given ratio can be generated in multiple ways,

allowing the user to stay within the operating frequency

ranges of the PLL. For example, in this case the input

divider could have been two and the output divider also

two, giving us a division of the input frequency by four

to go with the feedback loop division (effective

multiplication) by five.

Adjustable Clock Delay

Figure 2-15 on page 2-15 illustrates the delay of the

input clock by employing one of the adjustable delay

lines. This is easily done in ProASICPLUS by bypassing the

PLL core entirely and using the output delay line. Notice

also that the output clock can be effectively advanced

relative to the input clock by using the delay line in the

feedback path. This is shown in Figure 2-16 on page 2-15.

Clock Skew Minimization

Figure 2-17 on page 2-16 indicates how feedback from

the clock network can be used to create minimal skew

between the distributed clock network and the input

clock. The input clock is fed to the reference clock input

of the PLL. The output clock (GLA) feeds a clock network.

The feedback input to the PLL uses a clock input delayed

by a routing network. The PLL then adjusts the phase of

the input clock to match the delayed clock, thus

providing nearly zero effective skew between the two

clocks.

Refer

Actel's

Using

ProASICPLUS

Clock

Conditioning

Circuits

application

note

for

information.

Table 2-8 •

Clock Conditioning Circuitry Delay-Line

Settings

Delay Line

Delay Value (ns)

DLYB

+0.25

+0.50

3+4.0

DLYA

+0.25

+0.50

3+4.0

APA300 Datasheet(PDF) 23 Page - Actel Corporation

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