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APA600 Datasheet(PDF) 79 Page - Actel Corporation

Part # APA600
Description  ProASICPLUS짰 Flash Family FPGAs
PDF  178 Pages
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Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

APA600 Datasheet(HTML) 79 Page - Actel Corporation

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ProASICPLUS Flash Family FPGAs
v5.9
2-69
Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent)
Note: The plot shows the normal operation status.
Figure 2-42 • Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent)
Table 2-65 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/Industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
Description
Min.
Max.
Units
Notes
CCYC
Cycle time
7.5
ns
CMH
Clock high phase
3.0
ns
CML
Clock low phase
3.0
ns
ECBA
New EMPTY access from RCLKS
↓
3.0*
ns
FCBA
FULL
↓ access from RCLKS ↓
3.0*
ns
ECBH,
FCBH,
THCBH
Old EMPTY, FULL, EQTH, & GETH valid hold
time from RCLKS
↓
1.0
ns
Empty/full/thresh are invalid from the end
of hold until the new access is complete
OCA
New DO access from RCLKS
↑
7.5
ns
OCH
Old DO valid from RCLKS
↑
3.0
ns
RDCH
RDB hold from RCLKS
↑
0.5
ns
RDCS
RDB setup to RCLKS
↑
1.0
ns
RPCA
New RPE access from RCLKS
↑
9.5
ns
RPCH
Old RPE valid from RCLKS
↑
3.0
ns
HCBA
EQTH or GETH access from RCLKS
↓
4.5
ns
Note: *At fast cycles, ECBA and FCBA = MAX (7.5 ns – CMH), 3.0 ns.
RCLK
RPE
RDATA
EMPTY
EQTH, GETH
FULL
RDB
tRDCH
tOCH
tRPCH
tRDCS
OldDataOut
New Valid Data Out (Empty Inhibits Read)
Cycle Start
tECBH, tFCBH
tECBA, tFCBA
tOCA
tRPCA
tCMH
tCML
tCCYC
tTHCBH
tHCBA



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