APA600 datasheet(30/178 Pages) ACTEL

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ProASICPLUS Flash Family FPGAs

2- 20

v5.9

User Security

ProASICPLUS devices have FlashLock protection bits that,

once

programmed,

block

the

entire

programmed

contents from being read externally. Refer to Table 2-11

for details on the number of bits in the key for each

device. If locked, the user can only reprogram the device

employing the user-defined security key. This protects

the device from being read back and duplicated. Since

programmed data is stored in nonvolatile memory cells

(actually very small capacitors) rather than in the wiring,

physical deconstruction cannot be used to compromise

data. This type of security breach is further discouraged

by the placement of the memory cells beneath the four

metal layers (whose removal cannot be accomplished

without disturbing the charge in the capacitor). This is

the highest security provided in the industry. For more

information,

refer

Actel’s

Design

Security

Nonvolatile Flash and Antifuse FPGAs white paper.

Embedded Memory Floorplan

The embedded memory is located across the top and

bottom of the device in 256x9 blocks (Figure 1-1 on page

1-2). Depending on the device, up to 88 blocks are

available to support a variety of memory configurations.

Each block can be programmed as an independent

memory array or combined (using dedicated memory

routing resources) to form larger, more complex memory

configurations. A single memory configuration could

include blocks from both the top and bottom memory

locations.

Embedded Memory Configurations

The embedded memory in the ProASICPLUS family

provides great configuration flexibility (Table 2-12). Each

ProASICPLUS block is designed and optimized as a two-

port memory (one read, one write). This provides 198

kbits of two-port and/or single port memory in the

APA1000 device.

Each memory block can be configured as FIFO or SRAM,

with

independent

selection

synchronous

asynchronous

read

and

write

ports

(Table 2-13).

Additional characteristics include programmable flags as

well as parity checking and generation. Figure 2-18 on

page 2-22 and Figure 2-19 on page 2-23 show the block

diagrams of the basic SRAM and FIFO blocks. Table 2-14

on page 2-22 and Table 2-15 on page 2-23 describe

memory

block

SRAM

and

FIFO

interface

signals,

respectively. A single memory block is designed to

operate at up to 150 MHz (standard speed grade typical

conditions). Each block is comprised of 256 9-bit words

(one read port, one write port). The memory blocks may

be cascaded in width and/or depth to create the desired

memory organization. (Figure 2-20 on page 2-24). This

provides optimal bit widths of 9 (one block), 18, 36, and

72, and optimal depths of 256, 512, 768, and 1,024. Refer

to Actel’s SmartGen User’s Guide for more information.

Figure 2-21 on page 2-24 gives an example of optimal

memory usage. Ten blocks with 23,040 bits have been

used to generate three arrays of various widths and

depths. Figure 2-22 on page 2-24 shows how RAM blocks

can be used in parallel to create extra read ports. In this

example, using only 10 of the 88 available blocks of the

APA1000 yields an effective 6,912 bits of multiple port

RAM. The Actel SmartGen software facilitates building

wider and deeper memory configurations for optimal

memory usage.

Table 2-11 • Flashlock Key Size by Device

Device

Key Size

APA075

79 bits

APA150

79 bits

APA300

79 bits

APA450

119 bits

APA600

167 bits

APA750

191 bits

APA1000

263 bits

Table 2-12 • ProASICPLUS Memory Configurations by Device

Device

Bottom

Top

Maximum Width

Maximum Depth

DWDW

APA075

256

108

1,536

APA150

256

144

2,048

APA300

256

144

2,048

APA450

256

216

3,072

APA600

256

252

3,584

APA750

256

288

4,096

APA1000

256

396

5,632

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