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MP1493 Datasheet(PDF) 11 Page - Monolithic Power Systems

Part # MP1493
Description  3A, 4.2V-16V Input, Fast Transient Synchronous Step-down Converter
PDF  18 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP1493 Datasheet(HTML) 11 Page - Monolithic Power Systems

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MP1493 – 3A, 4.2V-16V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
MP1493 Rev. 1.15
www.MonolithicPower.com
11
12/9/2013
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
As can be seen from equation 7, if there is
instability in PWM mode, we can reduce either
R4 or C4. If C4 can not be reduced further due to
limitation from equation 4, then we can only
reduce R4. For a stable PWM operation, the
Vslope1 should be design follow equation 8.
SW
ON
-3
ESR
OUT
slope1
OUT
OUT
SW
on
TT
+-R
C
Io 10
0.7 π
2
-V
V
+
2L C
T -T
×
×
≥
××
(8)
Io is the load current.
In skip mode, the downward slope of the VFB
ripple is almost the same whether the external
ramp is used or not. Figure 7 shows the
simplified circuit of the skip mode when both the
HS-FET and LS-FET are off.
Figure 7—Simplified Circuit in skip Mode
The downward slope of the VFB ripple in skip
mode can be determined as follow:
()
REF
SLOPE2
12
OUT
V
V
(R
R // Ro) C
−
=
+×
(9)
Where Ro is the equivalent load resistor.
As described in Figure 4, VSLOPE2 in the skip mode
is lower than that is in the PWM mode, so it is
reasonable that the jitter in the skip mode is
larger. If one wants a system with less jitter
during ultra light load condition, the values of the
VFB resistors should not be too big, however, that
will decrease the ultra light load efficiency.
Soft Start/Stop
MP1493 employs soft start/stop (SS) mechanism
to ensure smooth output du ring power up and
power shut-down. When the EN pin becomes
high, an internal SS voltage ramps up slowly.
The SS voltage takes over the REF voltage to
the PWM comparator. The output voltage
smoothly ramps up with the SS voltage. Once SS
voltage reaches the same level of the REF
voltage, it keeps ramping up, while REF takes
over the PWM comparator. At this point, the soft
start finishes, it enters steady state operation.
The SS time is about 1ms.
When the EN pin becomes low, the internal SS
voltage is discharged through an internal current
source. Once the SS voltage reaches REF
voltage, it takes over the PWM comparator. The
output voltage will decrease smoothly with SS
voltage until zero level. s
Over-Current Protection (OCP) and Short-
Circuit Protection (SCP)
MP1493 has cycle-by cycle over-current limit
control. The inductor current is monitored during
the ON state. And it has two optional OCP/SCP
protection modes: latch-off mode and hiccup
mode.
For MP1493DS, the HS-FET turns off when the
inductor current exceeds the current limit and the
OCP timer—set at 50μs—starts. The OCP
triggers if the inductor current reaches or
exceeds the current limit every cycle in those
50μs. The MP1493DS short-circuit protection
(SCP) occurs when dead shorts occur—when the
inductor current exceeds the current limit and the
FB voltage is lower than 50% of the VREF—and
will trigger the OCP.
For MP1493DS-A, enters hiccup mode, that
periodically restarts the part when the inductor
current peak value exceeds the current limit and
VFB drops below the under-voltage (UV) threshold.
Typically, the UV threshold is 50% below the
REF voltage. In OCP/SCP, MP1493DS-A will
disable the output voltage power, discharge
internal soft-start cap, and then automatically try
to soft-start again. If the over-current circuit
condition still holds after soft-start ends, it
repeats this operation cycle until the over-current
circuit condition disappears, and output rises
back to regulation level.
Over/Under-voltage Protection (OVP/UVP)
MP1493 monitors the output voltage through a
resistor divided feedback (FB) voltage to detect
over and under voltage on the output. When the
FB voltage is higher than 125% of the REF
voltage, it’ll trigger OVP. Once it triggers OVP,
the LS-FET is always on, while the HS-FET is off.
It needs power cycle to power up again. When



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