LM2512A

SNLS269B – AUGUST 2007 – REVISED MAY 2013

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OPTIONAL LOOK UP TABLE AND SPI INTERFACE

Three 256 X 8-bit SRAMs provide a Look Up Table for independent color correction. The LUT is disabled by

default and also after a device PD* cycle. The PD* cycle can be entered via the PD* input pin directly, or by

stopping the PCLK. Before using the LUT, the SRAM must be loaded with its contents. If power is cycled to the

device, the LUT must be loaded again.

To enable the LUT:

1. Select/Unlock the LM2512A SPI Interface - Write FF’h to REG22 (16’h)

2. Write the LUT contents to the SRAM using Writes or Page Writes

3. Enable the LUT - Write a 01’h to REG0 (00’h)

4. De-Select/Lock the LM2512A SPI interface -Write 00’h to REG22 (16’h)

When waking up the LM2512A from the power down mode (PD*=L), the LUT needs to be enabled if it is desired.

Contents to the SRAM are still held and valid.

1. Select/Unlock the LM2512A SPI Interface - Write FF’h to REG22 (16’h)

2. Enable the LUT - Write a 01’h to REG0 (00’h)

3. Optional -select Lane Scale if not using default

4. De-Select/Lock the LM2512A SPI interface -Write a 00’h to REG22 (16’h)

If power is cycled to the device, the LUT SRAMs must be loaded again.

SPI Interface

The Serial Peripheral Interface (SPI) allows control over various aspects of the LM2512A, the Look Up Table

operation, and access to the three 256 x 8-RAM blocks. There are 9 defined registers in the device. Three SPI

transactions are supported, which are: 16-bit WRITE, PAGE WRITE, and a 16-bit READ. The SPI interface is

disabled when the device is in the sleep mode (via PCLK Stop or by PD* = L). The SPI interface may be used

when PD* = H.

16-bit WRITE

The 16-bit WRITE is shown in Figure 15. The SDA payload consists of a "0" (Write Command), seven address

bits and eight data bits. The CSX signal is driven Low, and 16-bits of SDA (data) are sent to the device. Data is

latched on the rising edge of the SCL. After each 16-bit WRITE, CSX must return HIGH.

Table 2. 16-bit WRITE – SPI

Bit

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

SDA

0

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

16-bit READ

The 16-bit READ is shown in Figure 16. The SDA payload consists of a "1" (Read Command), seven address

bits and eight data bits which are driven from the device. The CSX signal is driven Low, and the host drives the

first 8 bits of the SDA ("1" and seven address bits), the device then drives the respective 8 bits of the data on the

SDA signal.

Table 3. 16-bit READ – SPI

Bit

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

SDA

1

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

PAGE WRITE

The PAGE WRITE is shown in Figure 17. The SDA payload consists of a "0" (Write Command), seven address

bits of the start address and then the consecutive data bytes. 256 bytes maximum can be sent. The CSX signal

is driven Low, and the host drives the SDA signal with a "0" (Write Command), the seven start address bits and

the variable length data bytes. The Page Write is denoted by the CSX signal staying low while the data bytes are

streamed. Data is latched on the rising edge of the SCL.

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