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LM2512ASM Datasheet(PDF) 17 Page - Texas Instruments

Part # LM2512ASM
Description  LM2512A Mobile Pixel Link (MPL-1), 24 Bit RGB Display Interface Serializer with Optional Dithering and Look Up Table
PDF  28 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

LM2512ASM Datasheet(HTML) 17 Page - Texas Instruments

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LM2512A
MPL-1
DES
MDO
MD1
MC
MD2
MDO
MD1
MC
MD2
MD3 (NC)
LM2512A
FPD95320,
DES
MDO (NC)
MD1
MC
MD2
MD0
MC
MD1
MPL-1
DES
MD1
MC
MD2
LM2512A
www.ti.com
SNLS269B – AUGUST 2007 – REVISED MAY 2013
Take care in reviewing the MPL signals and serial bit mapping to ensure proper connection between the devices.
Figure 20. Application Configurations
LM2512A OPERATION
POWER SUPPLIES
The VDD and VDDA (MPL and PLL) must be connected to the same potential between 1.6V and 2.0V. VDDIO
powers the logic interface and may be powered between 1.6V and 3.0V to be compatible with a wide range of
host and target devices.
VDD/VDDA should be powered ON at the same time as VDDIO or before. VDDIO then VDD/VDDA is not recommended.
BYPASS RECOMMENDATIONS
Bypass capacitors should be placed near the power supply pins of the device. Use high frequency ceramic
(surface mount recommended) 0.1 µF capacitors. A 2.2 to 4.7 µF Tantalum capacitor is recommended near the
SER VDDA pin for PLL bypass. Connect bypass capacitors with wide traces and use dual or larger via to reduce
resistance and inductance of the feeds. Utilizing a thin spacing between power and ground planes will provide
good high frequency bypass above the frequency range where most typical surface mount capacitors are less
effective. To gain the maximum benefit from this, low inductance feed points are important. Also, adjacent signal
layers can be filled to create additional capacitance. Minimize loops in the ground returns also for improved
signal fidelity and lowest emissions.
UNUSED/OPEN PINS
Unused inputs must be tied to the proper input level—do not float them.
PHASE-LOCKED LOOP
A PLL is enabled to generate the serial link clock. The Phase-locked loop system generates the serial data clock
at 4X or 6X of the input clock depending upon the number of MD Lanes selected. The MC rate is limited to 80
MHz for this enhanced Class 0 MPL PHY.
POWER DOWN/OFF CONFIGURATION / OPTIONS AND CLOCK STOP
The LM2512A (SER) can be controlled by it’s PD* input pin or via a auto power down mode that monitors the
PCLK input signal.
For PD* Input Power Down control, a GPO signal from the host is used to enable and disable the LM2512A and
the DES. The LM2512A is enabled when the PD* input is High and disabled when the PD* input is Low.
Copyright © 2007–2013, Texas Instruments Incorporated
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Product Folder Links: LM2512A



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