AM186 datasheet(31/112 Pages) AMD

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Am186TMER and Am188TMER Microcontrollers Data Sheet

DRAF

ALE

Address Latch Enable (output, synchronous)

This pin indicates to the system that an address ap-

pears on the address and data bus (AD15–AD0 for

the Am186ER microcontroller or AO15–AO8 and

AD7–AD0 for the Am188ER microcontroller). The ad-

dress is guaranteed valid on the trailing edge of ALE.

This pin is three-stated during ONCE mode.

ARDY

Asynchronous Ready (input, asynchronous,

level-sensitive)

This pin indicates to the microcontroller that the ad-

dressed memory space or I/O device will complete a

data transfer. The ARDY pin accepts a rising edge that

is asynchronous to CLKOUTA and is active High. The

falling edge of ARDY must be synchronized to

CLKOUTA. To always assert the ready condition to the

microcontroller, tie ARDY High. If the system does not

use ARDY, tie the pin Low to yield control to SRDY.

BHE/ADEN

(Am186™ER Microcontroller Only)

Bus High Enable (three-state, output, synchronous)

Address Enable (input, internal pullup)

BHE—During a memory access, this pin and the least-

significant address bit (AD0 or A0) indicate to the sys-

tem which bytes of the data bus (upper, lower, or both)

participate in a bus cycle. The BHE/ADEN and AD0

pins are encoded as shown in Table 2.

BHE is asserted during t1 and remains asserted

through t3 and tW. BHE does not need to be latched.

BHE is three-stated during bus hold and reset condi-

tions.

On the Am186ER microcontroller, WLB and WHB im-

plement the functionality of BHE and AD0 for high and

low byte write enables.

Table 2.

Data Byte Encoding

BHE/ADEN also signals DRAM refresh cycles when

using the multiplexed address and data (AD) bus. A re-

fresh cycle is indicated when both BHE/ADEN and AD0

are High. During refresh cycles, the A bus and the AD

bus are not guaranteed to provide the same address

during the address phase of the AD bus cycle. For this

reason, the A0 signal cannot be used in place of the

AD0 signal to determine refresh cycles. PSRAM re-

freshes also provide an additional RFSH signal (see

the MCS3/RFSH pin description on page 33).

ADEN—If BHE/ADEN is held High or left floating dur-

ing power-on reset, the address portion of the AD bus

(AD15–AD0) is enabled or disabled during LCS and

UCS bus cycles based on the DA bit in the LMCS and

UMCS registers. If the DA bit is set, the memory ad-

dress is accessed on the A19–A0 pins. This mode of

operation reduces power consumption. For more infor-

mation, see the Bus Operation section on page 41.

There is a weak internal pullup resistor on BHE/ADEN

so no external pullup is required.

If BHE/ADEN is held Low on power-on reset, the AD

bus drives both addresses and data. Changing the DA

bit of the LMCS and UMCS registers will have no effect.

(S6 and UZI also assume their normal functionality in

this instance. The PIO Mode and Direction registers

cannot reconfigure these pins as PIOs. See Table 3 on

page 36.) The pin is sampled within three crystal clock

cycles after the rising edge of RES. BHE/ADEN is

three-stated during bus holds and ONCE mode.

Note: Once the above modes are set, they can be

changed only by resetting the processor.

CLKOUTA

Clock Output A (output, synchronous)

This pin supplies the internal clock to the system. De-

pending on the value of the Power-Save Control Regis-

ter (PDCON), CLKOUTA operates at either the CPU

fundamental frequency (which varies with the divide by

two, times one, and times four clocking modes), the

power-save frequency, or is three-stated (see Figure 10

on page 48). CLKOUTA remains active during reset

and bus hold conditions.

CLKOUTB

Clock Output B (output, synchronous)

This pin supplies a clock to the system. Depending on

the value of the Power-Save Control Register (PD-

CON), CLKOUTB operates at either the CPU funda-

mental frequency (which varies with the divide by two,

times one, and times four clocking modes), the power-

save frequency, or is three-stated (see Figure 10 on

page 48). CLKOUTB remains active during reset and

bus hold conditions.

DEN/PIO5

Data Enable (output, three-state, synchronous)

This pin supplies an output enable to an external data-

bus transceiver. DEN is asserted during memory, I/O,

and interrupt acknowledge cycles. DEN is deasserted

when DT/R changes state. DEN is three-stated during

a bus hold or reset condition.

BHE

AD0 Type of Bus Cycle

Word Transfer

High Byte Transfer (Bits 15–8)

Low Byte Transfer (Bits 7–0)

Refresh

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