AM186 datasheet(34/112 Pages) AMD

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Am186TMER and Am188TMER Microcontrollers Data Sheet

DRAF

MCS2–MCS0

(MCS2/PIO24, MCS1/PIO15, MCS0/PIO14)

Midrange Memory Chip Selects (output,

synchronous, internal pullup)

These pins indicate to the system that a memory ac-

cess is in progress to the corresponding region of the

midrange memory block. The base address and size of

the midrange memory block are programmable.

MCS2–MCS0 are held High during a bus hold condi-

tion. In addition, they have weak internal pullup resis-

tors that are active during reset. Unlike the UCS and

LCS chip selects, the MCS outputs assert with the mul-

tiplexed AD address bus.

NMI

Nonmaskable Interrupt (input, synchronous, edge-

sensitive)

This pin indicates to the microcontroller that an inter-

rupt request has occurred. The NMI signal is the high-

est priority hardware interrupt and, unlike the INT4–

INT0 pins, cannot be masked. The microcontroller al-

ways transfers program execution to the location spec-

ified by the nonmaskable interrupt vector in the

microcontroller interrupt vector table when NMI is as-

serted.

Although NMI is the highest priority interrupt source, it

does not participate in the priority resolution process of

the maskable interrupts. There is no bit associated with

NMI in the interrupt in-service or interrupt request reg-

isters. This means that a new NMI request can interrupt

an executing NMI interrupt service routine. As with all

hardware interrupts, the IF (interrupt flag) is cleared

when the processor takes the interrupt, disabling the

maskable interrupt sources. However, if maskable in-

terrupts are reenabled by software in the NMI interrupt

service routine, via the STI instruction for example, an

NMI currently in service will not have any effect on the

priority resolution of maskable interrupt requests. For

this reason, it is strongly advised that the interrupt ser-

vice routine for NMI does not enable the maskable in-

terrupts.

An NMI transition from Low to High is latched and syn-

chronized internally, and it initiates the interrupt at the

next instruction boundary. To guarantee that the inter-

rupt is recognized, the NMI pin must be asserted for at

least one CLKOUTA period. Because NMI is rising

edge sensitive, holding the pin High during reset has no

effect on program execution.

PCS3–PCS0

(PCS3/PIO19, PCS2/PIO18,

PCS1/PIO17, PCS0/PIO16)

Peripheral Chip Selects (output, synchronous)

These pins indicate to the system that a memory ac-

cess is in progress to the corresponding region of the

peripheral memory block (either I/O or memory ad-

dress space). The base address of the peripheral

memory block is programmable. PCS3–PCS0 are held

High during a bus hold condition. They are also held

High during reset.

PCS4 is not available on the Am186ER and Am188ER

microcontrollers.

Unlike the UCS/LCS chip selects, the PCS outputs as-

sert with the multiplexed AD address bus. Note also

that each peripheral chip select asser ts over a

256-byte address range, which is twice the address

range covered by peripheral chip selects in the

80C186/80C188 microcontrollers.

PCS5/A1/PIO3

Peripheral Chip Select 5 (output, synchronous)

Latched Address Bit 1 (output, synchronous)

PCS5—This pin indicates to the system that a memory

access is in progress to the sixth region of the periph-

eral memory block (either I/O or memory address

space). The base address of the peripheral memory

block is programmable. PCS5 is held High during a bus

hold condition. It is also held High during reset.

Unlike the UCS and LCS chip selects, the PCS outputs

assert with the multiplexed AD address bus. Note also

that each peripheral chip select asser ts over a

256-byte address range, which is twice the address

range covered by peripheral chip selects in the 80C186

and 80C188 microcontrollers.

A1—When the EX bit in the MCS and PCS auxiliary

dress bit 1 to the system. During a bus hold condition,

A1 retains its previously latched value.

PCS6/A2/PIO2

Peripheral Chip Select 6 (output, synchronous)

Latched Address Bit 2 (output, synchronous)

PCS6—This pin indicates to the system that a memory

access is in progress to the seventh region of the pe-

ripheral memory block (either I/O or memory address

space). The base address of the peripheral memory

block is programmable. PCS6 is held High during a bus

hold condition or reset.

Unlike the UCS and LCS chip selects, the PCS outputs

assert with the multiplexed AD address bus. Note also

that each peripheral chip select asser ts over a

256-byte address range, which is twice the address

range covered by peripheral chip selects in earlier gen-

erations of the Am186/Am188 microcontrollers.

A2—When the EX bit in the MCS and PCS auxiliary

dress bit 2 to the system. During a bus hold condition,

A2 retains its previously latched value.

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