AD9851FSPCB datasheet(12/24 Pages) AD

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AD9851

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THEORY OF OPERATION AND APPLICATION

The AD9851 uses direct digital synthesis (DDS) technology,

in the form of a numerically controlled oscillator (NCO), to

generate a frequency/phase-agile sine wave. The digital sine

wave is converted to analog form via an internal 10-bit high

speed D/A converter. An on-board high speed comparator

is provided to translate the analog sine wave into a low-jitter

TTL/CMOS-compatible output square wave. DDS technol-

ogy is an innovative circuit architecture that allows fast and

precise manipulation of its output word, under full digital con-

trol. DDS also enables very high resolution in the incremental

selection of output frequency. The AD9851 allows an output

frequency resolution of approximately 0.04 Hz at an 180 MSPS

clock rate with the option of directly using the reference clock or

by engaging the 6 REFCLK multiplier. The AD9851’s out-

put waveform is phase-continuous from one output frequency

change to another.

The basic functional block diagram and signal flow of the

AD9851 configured as a clock generator is shown in Figure 11.

The DDS circuitry is basically a digital frequency divider function

whose incremental resolution is determined by the frequency of

the system clock, and N (number of bits in the tuning word). The

phase accumulator is a variable-modulus counter that increments

the number stored in it each time it receives a clock pulse. When

the counter reaches full-scale it wraps around, making the phase

accumulator’s output phase-continuous. The frequency tuning

word sets the modulus of the counter, which effectively determines

the size of the increment ( Phase) that will be added to the value

in the phase accumulator on the next clock pulse. The larger

the added increment, the faster the accumulator wraps around,

which results in a higher output frequency.

The AD9851 uses an innovative and proprietary angle rotation

algorithm that mathematically converts the 14-bit truncated

value of the 32-bit phase accumulator to the 10-bit quantized

amplitude that is passed to the DAC.This unique algorithm uses a

much-reduced ROM look-up table and DSP to perform this func-

tion.This contributes to the small size and low power dissipation of

the AD9851.

The relationship between the output frequency, system clock, and

tuning word of the AD9851 is determined by the expression:

fOUT

= (

OUT



= (

= ( Phase  System Clock)/232

where



Phase = decimal value of 32-bit frequency tuning word.

System Clock = direct input reference clock (in MHz) or 6 the

input clock (in MHz) if the 6 REFCLK multiplier is engaged.

fOUT

= frequency of the output signal in MHz.

OUT

The digital sine wave output of the DDS core drives the internal

high speed 10-bit D/A converter that will construct the sine wave

in analog form.This DAC has been optimized for dynamic per-

formance and low glitch energy, which results in the low spurious

and jitter performance of the AD9851.The DAC can be operated

in either the single-ended (Figures 2 and 8) or differential output

configuration (Figures 9 and 10). DAC output current and RSET

values are determined using the following expressions:

IOUT

= 39.93/

OUT

RSET

RSET = 39.93/

SET

IOUT

Since the output of the AD9851 is a sampled signal, its output

spectrum follows the Nyquist sampling theorem. Specifically,

its output spectrum contains the fundamental plus aliased sig-

nals (images) that occur at integer multiples of the system clock

frequency ± the selected output frequency. A graphical repre-

sentation of the sampled spectrum, with aliased images, is shown

in Figure 12. Normal usable bandwidth is considered to extend

from dc to 1/2 the system clock.

CLOCK

OUT

AMPLITUDE/SINE

CONV ALGORITHM

PHASE

ACCUMULATOR

DDS CIRCUITRY

D/A

CONVERTER

COMPARATOR

REFERENCE

CLOCK

TUNING WORD SPECIFIES

OUTPUT FREQUENCY AS A

FRACTION OF REF CLOCK

FREQUENCY

IN DIGITAL

DOMAIN

120MHz

2ND IMAGE

FOUT

FC+FO

2FC–FO

2FC+FO

3FC–FO

180MHz

3RD IMAGE

220MHz

4TH IMAGE

280MHz

5TH IMAGE

80MHz

1ST IMAGE

20MHz

0Hz

(DC)

FC–FO

SIN (X)/ ENVELOPE

 = ()F/FC

100MHz

SYSTEM CLOCK FREQUENCY

Figure 12. Output Spectrum of a Sampled Sin(x)/x Signal

REV. D

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