AD9851FSPCB datasheet(13/24 Pages) AD

13 / 24 page

AD9851

–13–

In the example shown in Figure 12, the system clock is 100 MHz

and the output frequency is set to 20 MHz. As can be seen, the

aliased images are very prominent and of a relatively high energy

level as determined by the sin(x)/x rolloff of the quantized

D/A converter output. In fact, depending on the f/system clock

relationship, the first aliased image can equal the fundamental

amplitude (when fOUT

amplitude (when f

= 1/2 system clock). A low-pass filter is

generally placed between the output of the D/A converter and the

input of the comparator to suppress the jitter-producing effects

of nonharmonically related aliased images and other spurious

signals. Consideration must be given to the relationship of the

selected output frequency, the system clock frequency, and alias

frequencies to avoid unwanted output anomalies.

Images need not be thought of as useless by-products of a

DAC. In fact, with bandpass filtering around an image and

some amount of post-filter amplification, the image can become

the primary output signal (see Figure 8). Since images are not

harmonics, they retain a 1:1 frequency relationship to the fun-

damental output.That is, if the fundamental is shifted 1 kHz,

then the image is also shifted 1 kHz.This relationship accounts

for the frequency stability of an image, which is identical to that

of the fundamental. Users should recognize that the lower image

of an image pair surrounding an integer multiple of the system

clock will move in a direction opposite to that of the funda-

mental. Images of an image pair located above an integer multiple

of the system clock will move in the same direction as a fundamen-

tal movement.

The frequency band where images exist is much richer in spu-

rious signals and, therefore, more hostile in terms of SFDR.

Users of this technique should empirically determine what fre-

quencies are usable if their SFDR requirements are demanding.

A good rule-of-thumb for applying the AD9851 as a clock gen-

erator is to limit the fundamental output frequency to 40% of

reference clock frequency to avoid generating aliased signals that

are too close to the output band of interest (generally dc—

highest selected output frequency) to be filtered.This practice

will ease the complexity and cost of the external filter require-

ment for the clock generator application.

The reference clock input of the AD9851 has a minimum limi-

tation of 1 MHz without 6 REFCLK multiplier engaged and

5 MHz with multiplier engaged. The device has internal circuitry

that senses when the clock rate has dropped below the minimum

and automatically places itself in the power-down mode. In this

mode, the on-chip comparator is also disabled. This is important

information for those who may wish to use the on-chip compara-

tor for purposes other than squaring the DDS sine wave output.

When the clock frequency returns above the minimum threshold,

the device resumes normal operation after 5 µs (typically). This

shutdown mode prevents excessive current leakage in the dynamic

registers of the device.

The impact of reference clock phase noise in DDS systems is

actually reduced, since the DDS output is the result of a division

of the input frequency. The amount of apparent phase noise

reduction, expressed in dB, is found using 20 log fOUT

reduction, expressed in dB, is found using 20 log f

/fCLK

/f/f

where fOUT

where f

is the fundamental DDS output frequency and fCLK

is the fundamental DDS output frequency and f

CLK

the system clock frequency. From this standpoint, using the high-

est system clock input frequency makes good sense in reducing the

effects of reference clock phase noise contribution to the output

signals’ overall phase noise. As an example, an oscillator with

–100 dBc phase noise operating at 180 MHz would appear as a

–125 dB contribution to DDS overall phase noise for a 10 MHz

output. Engaging the 6 REFCLK multiplier has generally been

found to increase overall output phase noise.This increase is due

to the inherent 6 (15.5 dB) phase gain transfer function of the

6 REFCLK multiplier, as well as noise generated internally by

the clock multiplier circuit. By using a low phase noise reference

clock input to the AD9851, users can be assured of better than

–100 dBc/Hz phase noise performance for output frequencies

up to 50 MHz at offsets from 1 kHz to 100 kHz.

Programming the AD9851

The AD9851 contains a 40-bit register that stores the 32-bit

frequency control word, the 5-bit phase modulation word,

6 REFCLK multiplier, enable, and the power-down func-

tion. This register can be loaded in parallel or serial mode. A

logic high engages functions; for example, to power-down the

IC (sleep mode), a logic high must be programmed in that bit

location. Those users who are familiar with the AD9850 DDS

will find only a slight change in programming the AD9851,

specifically, data[0] of W0 (parallel load) and W32 (serial load)

now contains a 6 REFCLK multiplier enable bit that needs

to be set high to enable or low to disable the internal reference

clock multiplier.

Note: setting data[1] high in programming word W0 (parallel

mode) or word W33 high in serial mode is not allowed (see

Tables I and III).This bit controls a factory test mode that will

cause abnormal operation in the AD9851 if set high. If erro-

neously entered (as evidenced by Pin 2 changing from an input

pin to an output signal), an exit is provided by asserting RESET.

Unintentional entry to the factory test mode can occur if an

FQ_UD pulse is sent after initial power-up and RESET of the

AD9851. Since RESET does not clear the 40-bit input register,

this will transfer the random power-up values of the input register

to the DDS core.The random values may invoke the factory test

mode or power-down mode. Never issue an FQ_UD command if

the 40-bit input register contents are unknown.

In the default parallel load mode, the 40-bit input register is loaded

using an 8-bit bus. W_CLK is used to load the register in five

iterations of eight bytes. The rising edge of FQ_UD transfers the

contents of the register into the device to be acted upon and resets

the word address pointer to W0. Subsequent W_CLK rising edges

load 8-bit data, starting at W0 and then move the word pointer

to the next word. After W0 through W4 are loaded, additional

W_CLK edges are ignored until either a RESET is asserted or an

FQ_UD rising edge resets the address pointer to W0 in prepara-

tion for the next 8-bit load. See Figure 13.

In serial load mode, forty subsequent rising edges of W_CLK will

shift and load the 1-bit data on Pin 25 (D7) through the 40-bit

after the register is full will shift data out causing data that is left in

the register to be out-of-sequence and corrupted. The serial mode

must be entered from the default parallel mode (see Figure 17).

Data is loaded beginning with W0 and ending with W39. One

note of caution: the 8-bit parallel word (W0)—xxxxx011—that

parallel

invokes the serial mode should be overwritten with a valid 40-bit

serial word immediately after entering the serial mode to prevent

unintended engaging of the 6 REFCLK multiplier or entry into

REV. D

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