AD9851FSPCB datasheet(16/24 Pages) AD

16 / 24 page

AD9851

–16–

FQ UD

DATA

40 W

W CLK CYCLES

CLK CYCLES

W CLK

W39

Figure 19. Serial Load Frequency/Phase Update Sequence

Table III. 40-Bit Serial Load Word Functional Assignment

Freq–b0 (LSB)

Freq–b1

Freq–b2

Freq–b3

Freq–b4

Freq–b5

Freq–b6

Freq–b7

Freq–b8

Freq–b9

W10

Freq–b10

W11

Freq–b11

W12

Freq–b12

W13

Freq–b13

W14

Freq–b14

W15

Freq–b15

W16

Freq–b16

W17

Freq–b17

W18

Freq–b18

W19

Freq–b19

W20

Freq–b20

W21

Freq–b21

W22

Freq–b22

W23

Freq–b23

W24

Freq–b24

W25

Freq–b25

W26

Freq–b26

W27

Freq–b27

W28

Freq–b28

W29

Freq–b29

W30

Freq–b30

W31

Freq–b31 (MSB)

W32

6 REFCLK Multiplier Enable

W33

Logic 0*

W34

Power-Down

W35

Phase–b0 (LSB)

W36

Phase–b1

W37

Phase–b2

W38

Phase–b3

W39

Phase–b4 (MSB)

*This bit is always Logic 0.

Figure 20 shows a normal 40-bit serial word load sequence with

W33 always set to Logic 0 and W34 set to Logic 1 or Logic 0

to control the power-down function. The logic states of the

remaining 38 bits are unimportant and are marked with an X,

indicating “don’t care” status.To power down, set W34 = 1. To

power up from a powered down state, change W34 to Logic 0.

Wake-up from power-down mode requires approximately 5 µs.

Note:The 40-bit input register of the AD9851 is fully program-

mable while in the power-down mode.

FQ UD

W34 = 1

OR 0

DATA (7) –

40 W_CLK RISING EDGES

W CLK

W33 = 0

W35 = X

W39 = X

W38 = X

W0 = X

Figure 20. Serial Load Power-Down\Power-Up Sequence

IOUT

IOUTB

VDD

VINP/

VINN

VDD

a. DAC Output

c. Comparator Input

DIGITAL

OUT

VDD

DIGITAL

VDD

b. Comparator Output

d. Digital Input

Figure 21. I/O Equivalent Circuits

REV. D

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