LXT9785 datasheet(4/244 Pages) ETC2

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Cortina Systems® LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

LXT9785/LXT9785E

Datasheet

249241, Revision 12.0

04 November 2011

Contents

4.3.10 Global Hardware Control Interface ...................................................................... 147

4.3.11 FIFO Initial Fill Values.......................................................................................... 147

4.4

Operating Requirements................................................................................................... 148

4.4.1

Power Requirements ........................................................................................... 148

4.4.2

Clock/SYNC Requirements ................................................................................. 148

4.4.2.1

Reference Clock .................................................................................. 148

4.4.2.2

TxCLK Signal (SS-SMII only)............................................................... 148

4.4.2.3

TxSYNC Signal (SMII/SS-SMII)........................................................... 148

4.4.2.4

RxSYNC Signal (SS-SMII only) ........................................................... 148

4.4.2.5

RxCLK Signal (SS-SMII Only) ............................................................. 149

4.5

Initialization ....................................................................................................................... 149

4.5.1

MDIO Control Mode............................................................................................. 149

4.5.2

Hardware Control Mode....................................................................................... 149

4.5.3

Power-Down Mode .............................................................................................. 150

4.5.3.1

Global (Hardware) Power Down .......................................................... 151

4.5.3.2

Port (Software) Power Down ............................................................... 151

4.5.4

Reset ................................................................................................................... 151

4.5.5

Hardware Configuration Settings......................................................................... 151

4.6

Link Establishment............................................................................................................ 152

4.6.1

Auto-Negotiation .................................................................................................. 152

4.6.1.1

Base Page Exchange .......................................................................... 152

4.6.1.2

Manual Next Page Exchange .............................................................. 152

4.6.1.3

Controlling Auto-Negotiation ................................................................ 153

4.6.1.4

Link Criteria.......................................................................................... 153

4.6.1.5

Parallel Detection................................................................................. 153

4.6.1.6

Reliable Link Establishment While Auto MDI/MDIX is Enabled in Forced

Speed Mode......................................................................................... 154

4.7

Serial MII Operation.......................................................................................................... 154

4.7.1

SMII Reference Clock.......................................................................................... 157

4.7.2

TxSYNC Pulse (SMII/SS-SMII)............................................................................ 157

4.7.3

Transmit Data Stream.......................................................................................... 157

4.7.3.1

Transmit Enable................................................................................... 157

4.7.3.2

Transmit Error ...................................................................................... 157

4.7.4

Receive Data Stream........................................................................................... 158

4.7.4.1

Carrier Sense....................................................................................... 158

4.7.4.2

Receive Data Valid .............................................................................. 158

4.7.4.3

Receive Error ....................................................................................... 158

4.7.4.4

Receive Status Encoding..................................................................... 158

4.7.5

Collision ............................................................................................................... 158

4.7.6

Source Synchronous-Serial Media Independent Interface .................................. 159

4.8

RMII Operation ................................................................................................................. 162

4.8.1

RMII Reference Clock.......................................................................................... 162

4.8.2

Transmit Enable................................................................................................... 163

4.8.3

Carrier Sense & Data Valid.................................................................................. 163

4.8.4

Receive Error....................................................................................................... 163

4.8.5

Out-of-Band Signaling ......................................................................................... 163

4.9

100 Mbps Operation ......................................................................................................... 166

4.9.1

100BASE-X Network Operations......................................................................... 166

4.9.2

100BASE-X Protocol Sublayer Operations.......................................................... 166

4.9.2.1

PCS Sublayer ...................................................................................... 166

4.9.3

PMA Sublayer...................................................................................................... 167

4.9.3.1

Link ...................................................................................................... 168

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