LXT9785 datasheet(5/244 Pages) ETC2

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Cortina Systems® LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

LXT9785/LXT9785E

Datasheet

249241, Revision 12.0

04 November 2011

Contents

4.9.3.2

Link Failure Override............................................................................ 169

4.9.3.3

Carrier Sense/Data Valid (RMII) .......................................................... 169

4.9.3.4

Carrier Sense (SMII) ............................................................................ 169

4.9.3.5

Receive Data Valid (SMII).................................................................... 169

4.9.3.6

Twisted-Pair PMD Sublayer................................................................. 169

4.9.3.7

Fiber PMD Sublayer............................................................................. 170

4.10 10 Mbps Operation ...........................................................................................................171

4.10.1 Preamble Handling .............................................................................................. 171

4.10.2 Dribble Bits .......................................................................................................... 171

4.10.3 Link Test .............................................................................................................. 171

4.10.3.1 Link Failure .......................................................................................... 172

4.10.4 Jabber.................................................................................................................. 172

4.11 DTE Discovery Process.................................................................................................... 172

4.11.1 Definitions ............................................................................................................ 172

4.11.2 Interaction between Processor, MAC, and PHY.................................................. 173

4.11.3 Management Interface and Control ..................................................................... 174

4.11.4 DTE Discovery Process Flow .............................................................................. 175

4.11.5 DTE Discovery Behavior...................................................................................... 176

4.12 Monitoring Operations ...................................................................................................... 177

4.12.1 Monitoring Auto-Negotiation ................................................................................ 177

4.12.2 Per-Port LED Driver Functions ............................................................................ 178

4.12.3 Out-of-Band Signaling ......................................................................................... 179

4.12.4 Boundary Scan Interface ..................................................................................... 180

4.12.5 State Machine...................................................................................................... 180

4.12.6 Instruction Register.............................................................................................. 180

4.12.7 Boundary Scan Register...................................................................................... 180

4.13 Cable Diagnostics Overview............................................................................................. 181

4.13.1 Features............................................................................................................... 181

4.13.2 Operation ............................................................................................................. 181

4.13.2.1 Short and Long Cable Testing Requirements...................................... 181

4.13.2.2 Precision .............................................................................................. 181

4.13.3 Implementation Considerations ........................................................................... 182

4.13.4 Basic Implementation .......................................................................................... 182

4.14 Link Hold-Off Overview..................................................................................................... 183

4.14.1 Features............................................................................................................... 183

4.14.2 Operation ............................................................................................................. 184

5.0

Application Information ............................................................................................................ 185

5.1

Design Recommendations................................................................................................ 185

5.2

General Design Guidelines............................................................................................... 185

5.2.1

Power Supply Filtering......................................................................................... 185

5.2.2

Power and Ground Plane Layout Considerations................................................ 186

5.2.2.1

Chassis Ground ................................................................................... 186

5.2.3

MII Terminations .................................................................................................. 186

5.2.4

Twisted-Pair Interface.......................................................................................... 186

5.2.4.1

Magnetic Requirements ....................................................................... 187

5.2.5

The Fiber Interface .............................................................................................. 187

5.2.6

LED Circuit........................................................................................................... 188

5.3

Typical Application Circuits............................................................................................... 188

6.0

Test Specifications.................................................................................................................... 194

7.0

Register Definitions................................................................................................................... 214

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