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LXT9785 Datasheet(PDF) 46 Page - List of Unclassifed Manufacturers

Part # LXT9785
Description  Advanced 8-Port 10/100 Mbps PHY Transceivers
PDF  244 Pages
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LXT9785 Datasheet(HTML) 46 Page - List of Unclassifed Manufacturers

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Page 46
Cortina Systems® LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
LXT9785/LXT9785E
Datasheet
249241, Revision 12.0
04 November 2011
3.2 PQFP Signal Descriptions
Table 6
SMII/SS-SMII Common Signal Descriptions – PQFP
Pin/Ball
Designation
Symbol
Type1
Signal Description2
PQFP
PBGA
61
52
42
34
22
13
4
203
E2,
C3,
B5,
D8,
A11,
B13,
D13,
E14
TxData0
TxData1
TxData2
TxData3
TxData4
TxData5
TxData6
TxData7
I, ID
Transmit Data - Ports 0-7.
These serial input streams provide data to be transmitted to
the network. The LXT9785/LXT9785E clocks the data in
synchronously to REFCLK.
44
6
E6,
E12
REFCLK0
REFCLK1
I
Reference Clock.
The LXT9785/LXT9785E always requires a 125 MHz
reference clock input. Refer to Functional Description for
detailed clock requirements. REFCLK0 and REFCLK1 are
always connected regardless of sectionalization mode.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal
pull-Down.
2. The IP/ID resistors are disabled during H/W Power-Down mode.
Table 7
SMII Specific Signal Descriptions – PQFP
Pin/Ball
Designation
Symbol
Type1
Signal Description2,3
PQFP
PBGA
35
204
A6,
C16
SYNC0
SYNC1
I, ID
SMII Synchronization.
The MAC must generate a SYNC pulse every 10 REFCLK
cycles to synchronize the SMII. SYNC0 is used when 1x8
port sectionalization is selected. SYNC0 and SYNC1 are to
be used when 2x4 port sectionalization is chosen.
55
46
37
28
16
8
206
198
C2,
A3,
B6,
D9,
A13,
B14,
C15,
E16
RxData0
RxData1
RxData2
RxData3
RxData4
RxData5
RxData6
RxData7
O, TS
Receive Data - Ports 0-7.
These serial output streams provide data received from the
network. The LXT9785/LXT9785E drives the data out
synchronously to REFCLK.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal
pull-Down.
2. The IP/ID resistors are disabled during H/W Power-Down mode.
3. RxData[0:7] outputs are three-stated in Isolation and hardware power-down modes and during hardware
reset.



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