AM79C975VCW datasheet(32/304 Pages) AMD

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Am79C973/Am79C975

P R E L I M INARY

tus (see BCR4). The LED0 pin polarity is programma-

ble, but by default it is active LOW. When the LED0 pin

polarity is programmed to active LOW, the output is an

open drain driver. When the LED0 pin polarity is pro-

grammed to active HIGH, the output is a totem pole

driver.

Note: The LED0 pin is multiplexed with the EEDI pin.

LED1

Output

This output is designed to directly drive an LED. By de-

fault, LED1 indicates receive activity on the network.

This pin can also be programmed to indicate other net-

work status (see BCR5). The LED1 pin polarity is pro-

grammable, but by default, it is active LOW. When the

LED1 pin polarity is programmed to active LOW, the

output is an open drain driver. When the LED1 pin po-

larity is programmed to active HIGH, the output is a

totem pole driver.

Note: The LED1 pin is multiplexed with the EESK and

SFBD pins.

The LED1 pin is also used during EEPROM Auto-

Detection to determine whether or not an EEPROM is

present at the Am79C973/Am79C975 controller inter-

face. At the last rising edge of CLK while RST is active

LOW, LED1 is sampled to determine the value of the

EEDET bit in BCR19. It is important to maintain ade-

quate hold time around the rising edge of the CLK at

this time to ensure a correctly sampled value. A sam-

pled HIGH value means that an EEPROM is present,

and EEDET will be set to 1. A sampled LOW value

means that an EEPROM is not present, and EEDET

will be set to 0. See the EEPROM Auto-Detection sec-

tion for more details.

If no LED circuit is to be attached to this pin, then a pull

up or pull down resistor must be attached instead in

order to resolve the EEDET setting.

WARNING: The input signal level of LED1 must be

insured for correct EEPROM detection before the

deassertion of RST.

LED2

Output

This output is designed to directly drive an LED. This

pin can be programmed to indicate various network

status (see BCR6). The LED2 pin polarity is program-

mable, but by default it is active LOW. When the LED2

pin polarity is programmed to active LOW, the output is

an open drain driver. When the LED2 pin polarity is pro-

grammed to active HIGH, the output is a totem pole

driver.

Note: The

LED2

multiplexed

with

the

MIIRXFRTGE pin.

LED3

Output

This output is designed to directly drive an LED. By de-

fault, LED3 indicates transmit activity on the network.

This pin can also be programmed to indicate other net-

work status (see BCR7). The LED3 pin polarity is pro-

grammable, but by default it is active LOW. When the

LED3 pin polarity is programmed to active LOW, the

output is an open drain driver. When the LED3 pin po-

larity is programmed to active HIGH, the output is a

totem pole driver.

Special attention must be given to the external circuitry

attached to this pin. When this pin is used to drive an

LED while an EEPROM is used in the system, then

buffering maybe required between the LED3 pin and

the LED circuit. If an LED circuit were directly attached

to this pin, it may create an IOL requirement that could

not be met by the serial EEPROM attached to this pin.

If no EEPROM is included in the system design or low

current LEDs are used, then the LED3 signal may be

directly connected to an LED without buffering. For

more details regarding LED connection, see the sec-

tion on LED Support.

Note: The LED3 pin is multiplexed with the EEDO and

MIIRXFRTGD pins.

Power Good

Input

The PG pin has two functions: (1) it puts the device into

Magic Packet™ mode, and (2) it blocks any resets

when the PCI bus power is off.

When PG is LOW and either MPPEN or MPMODE is

set to 1, the device enters the Magic Packet mode.

When PG is LOW, a LOW assertion of the PCI RST pin

will only cause the PCI interface pins (except for PME)

to be put in the high impedance state. The internal logic

will ignore the assertion of RST.

When PG is HIGH, assertion of the PCI RST pin

causes the controller logic to be reset and the configu-

ration information to be loaded from the EEPROM.

PG input should be kept high during the NAND tree

testing.

RWU

Remote Wake Up

Output

RWU is an output that is asserted either when the con-

troller is in the Magic Packet mode and a Magic Packet

frame has been detected, or the controller is in the Link

Change Detect mode and a Link Change has been de-

tected.

This pin can drive the external system management

logic that causes the CPU to get out of a low power

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