AM79C975VCW datasheet(37/304 Pages) AMD

37 / 304 page

Am79C973/Am79C975

P R E L I M INARY

pins carry the transmit output data and are connected

to the transmit side of the magnetics module.

RX+, RX-

Serial Receive Data

MLT-3/PECL

Input

These pins are the 10BASE-T/100BASE-X port differ-

ential receiver pairs. They receive MLT-3 data and are

connected to the receive side of the magnetics module

in 100BASE-TX operation. They receive PECL NRZI

data from an exter nal fiber optic transceiver in

100BASE-FX application. For 10BASE-T, these pins

accept the receive input data from the magnetics mod-

ule.

SDI+, SDI-

Signal Detect

Input

These pins control the selection between PECL and

MLT-3 data for the TX± and RX± pins. For 100BASE-

TX or 10BASE-T, both of these pins may be tied to

ground or left floating. This enables transmission and

reception of MLT-3 or 10BASE-T signals at the TX± and

RX± pins. For 100BASE-FX, these pins are biased at

PECL levels. They are connected to the SDI pin from

the optical transceiver module to indicate whether the

received signal is above the required threshold. If sig-

nal detect is not available, these pins should be tied to

a PECL logical 1 (SDI+ = PECL 1, SDI- = PECL 0). See

Table 2.

Table 2. SDI± Settings for Transceiver Operation

IREF

Internal Current Reference

Input

This pin serves as a current reference for the integrated

10/100 PHY. It must be connected to ground via a

12 k

Ω resistor (1%).

Clock Interface

XTAL1

Crystal Input

Input

The internal clock generator uses a 25-MHz (50 ppm-

100 ppm) crystal that is attached to the XTAL1 and

XTAL2 pins. XTAL1 may alternatively be driven using

an external 25 MHz (50 ppm - 100 ppm) CMOS-level

clock signal when XTAL2 is left floating. The XTAL1 pin

is not 5 V tolerant and must only be driven by a 3.3 V

clock source.

XTAL2

Crystal Output

Output

The internal clock generator uses a 25 MHz (50 ppm -

100 ppm) crystal that is attached to the pins XTAL1 and

XTAL2. XTAL1 may alternatively be driven using an ex-

ternal 25 MHz (50 ppm - 100 ppm) CMOS-level clock

signal when XTAL2 is left floating.

XCLK/XTAL

External Clock/Crystal Select

Input

When HIGH, an External Clock Source is selected by-

passing the Crystal circuit. When LOW, a Crystal is

used instead. The following table illustrates how this pin

works.

Serial Management Interface (SMI)

(Am79C975 only)

MCLOCK

SMI Clock

Input/Output

MCLOCK is the clock pin of the serial management in-

terface. MCLOCK is typically driven by an external I2C/

SMBus master. The Am79C975 controller will drive the

clock line low in order to insert wait states before it

starts sending out data in response to a read. The fre-

quency of the clock signal can vary between 10 kHz

and 100 kHz, and it can change from cycle to cycle.

Note: MCLOCK is also capable of running at a fre-

quency as high as 2.5 MHz to allow for shorter produc-

tion test time.

MDATA

SMI Data

Input/Output

MDATA is the data pin of the serial management inter-

face. MDATA can be driven by an external I2C/SMBus

master or by the Am79C975 controller. The interface

protocol defines exactly at what time the Am79C975

controller has to listen to the MDATA pin and at what

time the controller must drive the pin.

MIRQ

SMI Interrupt

Output

MIRQ is an asynchronous attention signal that the

Am79C975 controller provides to indicate that a man-

agement frame has been transmitted or received. The

assertion of the MIRQ signal can be controlled by a glo-

bal mask bit (MIRQEN) or individual mask bits

SDI+

SDI-

Port Mode

TTL LOW

(<0.8 V)

TTL LOW

(<0.8 V)

MLT-3/10BASE-T

Mode

TTL HIGH

(>2.0 V)

TTL HIGH

(>2.0 V)

PECL Mode

Input Pin

Output

XCLK/XTAL

Clock Source

XATL1

XTAL2

Crystal

XTAL1

Don’t Care

Oscillator/

External CLK

Source

AM79C975VCW Datasheet(PDF) 37 Page - Advanced Micro Devices

AM79C975VCW Datasheet(HTML) 37 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL