AM79C975VCW datasheet(43/304 Pages) AMD

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Am79C973/Am79C975

P R E L I M INARY

Expansion ROM Transfers

The host must initialize the Expansion ROM Base Ad-

dress register at offset 30H in the PCI configuration

space with a valid address before enabling the access

to the device. The Am79C973/Am79C975 controllers

will not react to any access to the Expansion ROM until

both MEMEN (PCI Command register, bit 1) and

ROMEN (PCI Expansion ROM Base Address register,

bit 0) are set to 1. After the Expansion ROM is enabled,

the Am79C973/Am79C975 controllers will assert

DEVSEL on all memory read accesses with an address

between ROMBASE and ROMBASE + 1M - 4. The

Am79C973/Am79C975 controller aliases all accesses

to the Expansion ROM of the command types Memory

Read Multiple and Memory Read Line to the basic

Memory Read command. Eight-bit, 16-bit, and 32-bit

read transfers are supported.

Since setting MEMEN also enables memory mapped

access to the I/O resources, attention must be given

the PCI Memory Mapped I/O Base Address register

before enabling access to the Expansion ROM. The

host must set the PCI Memory Mapped I/O Base

Address r egister to a value that prevents the

Am79C973/Am79C975 controllers from claiming any

memory cycles not intended for it.

The Am79C973/Am79C975 controllers will always

read four bytes for every host Expansion ROM read ac-

cess. TRDY will not be asserted until all four bytes are

loaded into an internal scratch register. The cycle

TRDY is asserted depends on the programming of the

Expansion ROM interface timing. The following figure

(Figure 5) assumes that ROMTMG (BCR18, bits 15-

12) is at its default value.

Note: The Expansion ROM should be read only during

PCI configuration time for the PCI system.

When the host tries to write to the Expansion ROM, the

Am79C973/Am79C975 controllers will claim the cycle

by asserting DEVSEL. TRDY will be asserted one clock

cycle later. The write operation will have no effect.

Writes to the Expansion ROM are done through the

BCR30 Expansion Bus Data Port. See the section on

the Expansion Bus Interface for more details. See Fig-

ure 5.

Figure 5. Expansion ROM Read

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

PAR

ADDR

CMD

PAR

2345

DATA

PAR

DEVSEL

is sampled

21510D-10

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