AM79C975VCW datasheet(36/304 Pages) AMD

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Am79C973/Am79C975

P R E L I M INARY

Start of Frame Delimiter is driven on RXD[3:0], and

must remain asserted until after the rising edge of

RX_CLK, when the last nibble of the CRC is driven on

RXD[3:0]. RX_DV must then be deasserted prior to the

RX_CLK rising edge which follows this final nibble.

RX_DV transitions are synchronous to RX_CLK rising

edges.

Note: The

RX_DV

multiplexed

with

the

EBD4 pin.

External Address Detection Interface

EAR

External Address Reject Low

Input

The incoming frame will be checked against the inter-

nally active address detection mechanisms and the re-

sult of this check will be OR’d with the value on the EAR

pin. The EAR pin is defined as REJECT. The pin value

is OR’d with the internal address detection result to de-

termine if the current frame should be accepted or re-

jected.

The EAR pin must not be left unconnected, it should

be tied to VDD through a 10-k

Ω ±5% resistor.

When RST is active, EAR is an input for NAND tree

testing.

SFBD

Start Frame-Byte Delimiter

Output

An initial rising edge on the SFBD signal indicates that

a start of valid data is present on the RXD[3:0] pins.

SFBD will go high for one nibble time (400 ns when op-

erating at 10 Mbps and 40 ns when operating at 100

Mbps) one RX_CLK period after RX_DV has been as-

serted and RX_ER is deasserted and the detection of

the SFD (Start of Frame Delimiter) of a received frame.

Data on the RXD[3:0] will be the start of the destination

address field. SFBD will subsequently toggle every nib-

ble time (1.25 MHz frequency when operating at 10

Mbps and 12.5 MHz frequency when operating at 100

Mbps) indicating the first nibble of each subsequent

byte of the received nibble stream. The RX_CLK

should be used in conjunction with the SFBD to latch

the correct data for external address matching. SFBD

will be active only during frame reception.

Note: The SFBD pin is multiplexed with the EESK and

LED1 pins.

MIIRXFRTGD

MII Receive Frame Tag Enable

Input

When the EADI is enabled (EADISEL, BCR2, bit 3), the

Receive Frame Tagging is enabled (RXFRTG, CSR7,

bit 14), and the MII Snoop mode is selected, the MIIRX-

FRTGD pin becomes a data input pin for the Receive

Frame Tag. See the Receive Frame Tagging section for

details.

Note: The MIIRXFRTGD pin is multiplexed with the

EEDO and LED3 pins.

MIIRXFRTGE

MII Receive Frame Tag Enable

Input

When the EADI is enabled (EADISEL, BCR2, bit 3), the

Receive Frame Tagging is enabled (RXFRTG, CSR7,

bit 14), and the MII Snoop mode is selected, the MIIRX-

FRTGE pin becomes a data input enable pin for the Re-

ceive Frame Tag. See the Receive Frame Tagging

section for details.

Note: The MIIRXFRTGE pin is multiplexed with the

LED2 pin.

IEEE 1149.1 (1990) Test Access Port

Interface

TCK

Test Clock

Input

TCK is the clock input for the boundary scan test mode

operation. It can operate at a frequency of up to 10

MHz. TCK has an internal pull up resistor.

TDI

Test Data In

Input

TDI is the test data input path to the Am79C973/

Am79C975 controller. The pin has an internal pull up

resistor.

TDO

Test Data Out

Output

TDO is the test data output path from the Am79C973/

Am79C975 controller. The pin is tri-stated when the

JTAG port is inactive.

TMS

Test Mode Select

Input

A serial input bit stream on the TMS pin is used to de-

fine the specific boundary scan test to be executed.

The pin has an internal pull up resistor.

Network Interfaces

TX+, TX-

Serial Transmit Data

MLT-3/PECL

Output

These pins are the 10BASE-T/100BASE-X differential

drivers. For 100BASE-FX, these transmit outputs carry

differential PECL-level NRZI data for direct connection

to an external fiber optic transceiver. They can be

forced to logical 0 (TX+ low, TX- high) by programming

the TX_DISABLE bit (bit 3 of the internal PHY Control/

Status Register, Register 17). For 100BASE-TX, these

pins carry MLT-3 data and are connected to the primary

side of the magnetics module. For 10BASE-T, these

AM79C975VCW Datasheet(PDF) 36 Page - Advanced Micro Devices

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