ADS5287 datasheet(23/42 Pages) TI

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EN_SDR= '1',FALL_SDR='0'

EN_SDR= '1',FALL_SDR='1'

ADCLK

LCLK

OUT

ADCLK

LCLK

OUT

ADS5287

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SBAS428D – JANUARY 2008 – REVISED JUNE 2012

In addition to programming the phase of LCLK in the DDR mode, the device can also be made to operate in SDR

mode by setting the EN_SDR bit to '1'. In this mode, the bit clock (LCLK) is output at 12x times the input clock, or

twice the rate as in DDR mode. Depending on the state of FALL_SDR, LCLK may be output in either of the two

manners shown in Figure 3. As shown in Figure 3, only the LCLK rising (or falling) edge is used to capture the

output data in SDR mode.

Figure 3. SDR Interface Modes

The SDR mode does not work well beyond 40MSPS because the LCLK frequency becomes very high.

DATA OUTPUT FORMAT MODES

The ADC output, by default, is in straight offset binary mode. Programming the BTC_MODE bit to '1' inverts the

MSB, and the output becomes binary two's complement mode.

Also by default, the first two bits of the frame (following the rising edge of ADCLKP) are zeroes, followed by the

LSB of the ADC output. Programming the MSB_FIRST mode inverts the bit order in the word. Thus, in the

MSB_FIRST mode, the MSB is output as the first bit following the ADCLKP rising edge. The two zeroes come

after the LSB at the end of the word.

ADS5287 Datasheet(PDF) 23 Page - Texas Instruments