LM5088, LM5088-Q1

SNVS600H – DECEMBER 2008 – REVISED MARCH 2013

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A is the gain of the current sense amplifier (10V/V)

(3)

The RAMP capacitor should connected directly to the RAMP and GND pins of the IC.

For duty cycles greater than 50%, peak current mode control circuits are subject to sub-harmonic oscillation.

Sub-harmonic oscillation is normally characterized by alternating wide and narrow pulses at the SW pin. Adding

a fixed slope voltage ramp (slope compensation) to the current sense signal prevents this oscillation. The 25 µA

offset current supplied by the emulated current source provides a fixed slope to the ramp signal. In some high

output voltage, high duty cycles applications; additional slope compensation may be required. In these

applications, a pull-up resistor may be added between the RAMP and VCC pins to increase the ramp slope

compensation. A formula to configure pull-up resistor is shown in Applications Information.

Dropout Voltage Reduction

The LM5088 features unique circuitry to reduce the dropout voltage. Dropout voltage is defined as the difference

thus determines the lowest input voltage at which the converter maintains regulation. In a buck converter,

dropout voltage primarily depends upon the maximum duty cycle. The maximum duty cycle is dependant on the

oscillator frequency and minimum off-time.

An approximation for the dropout voltage is:

where

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(4)

From the above equation, it can be seen that for a given output voltage, reducing the dropout voltage requires

required to replenish the bootstrap capacitor and time required to sample the re-circulating diode current. The

365 ns forced off-time of the LM5088 controller is a good trade-off between these two requirements. Thus the

LM5088 reduces dropout voltage by dynamically decreasing the operating frequency during dropout. The

Dynamic Frequency Control (DFC) is achieved using a dropout monitor, which detects a dropout condition and

reduces the operating frequency. The operating frequency will continue to decrease with decreasing input

voltage until the frequency falls to the minimum value set by the DFC circuitry.

(5)

If the VIN voltage continues to fall below this point, output regulation can no longer be maintained. The oscillator

frequency will revert back to the nominal operating frequency set by the RT resistor when the input voltage

increases above the dropout range. DFC circuitry does not affect the PWM during normal operating conditions.

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