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AS1130

Datasheet - D e t a i l e d D e s c r i p t i o n

- Master Transmitter to Slave Receiver. The first byte transmitted by the master is the slave address, followed by a number of data bytes.

The slave returns an acknowledge bit after the slave address and each received byte.

- Slave Transmitter to Master Receiver. The first byte, the slave address, is transmitted by the master. The slave then returns an acknowl-

edge bit. Next, a number of data bytes are transmitted by the slave to the master. The master returns an acknowledge bit after all received

bytes other than the last byte. At the end of the last received byte, a not-acknowledge is returned. The master device generates all of the

serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or a repeated START condition. Since

a repeated START condition is also the beginning of the next serial transfer, the bus will not be released.

The AS1130 can operate in the following slave modes:

- Slave Receiver Mode. Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is trans-

mitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by

hardware after reception of the slave address and direction bit.

- Slave Transmitter Mode. The first byte (the slave address) is received and handled as in the slave receiver mode. However, in this mode

the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted on SDA by the AS1130 while the serial clock

is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer.

Command Byte

The AS1130 operation, (see Table 13 on page 20) is determined by a command byte (see Table 19).

Figure 19. Command Byte

Figure 20. Command and Single Data Byte received by AS1130

Figure 21. Setting the Pointer to a Address Register to select a Data Register for a Read Operation

A7

A6

A5

A4

A3

A2

A1

A0

MSB

6

5

4

3

2

1

LSB

From Master to Slave

From Slave to Master

A

A

P

A

S

Command Byte

Data Byte

Slave Address

A6

A5

A4

A3

A2

A1

A0

A7

D6

D5

D4

D3

D2

D1

D0

D7

Acknowledge

from AS1130

0

0

0

Acknowledge

from AS1130

Acknowledge

from AS1130

R/W

0

AS1130 Registers

Autoincrement

Memory Word

Address

1 Byte

From Master to Slave

From Slave to Master

A

P

A

S

Command Byte

Slave Address

A6

A5

A4

A3

A2

A1

A0

A7

0

0

Acknowledge

from AS1130

Acknowledge

from AS1130

R/W

0

AS1130 Registers