LF198JAN

SNOSAJ2A – FEBRUARY 2005 – REVISED MARCH 2013

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Differential Hold

Capacitor Hysteresis Compensation

**Adjust for amplitude

Definition of Terms

Hold Step: The voltage step at the output of the sample and hold when switching from sample mode to hold

mode with a steady (dc) analog input voltage. Logic swing is 5V.

Acquisition Time: The time required to acquire a new analog input voltage with an output step of 10V. Note that

acquisition time is not just the time required for the output to settle, but also includes the time required for all

internal nodes to settle so that the output assumes the proper value when switched to the hold mode.

Gain Error: The ratio of output voltage swing to input voltage swing in the sample mode expressed as a per cent

difference.

Hold Settling Time: The time required for the output to settle within 1 mV of final value after the “hold” logic

command.

Dynamic Sampling Error: The error introduced into the held output due to a changing analog input at the time

the hold command is given. Error is expressed in mV with a given hold capacitor value and input slew rate. Note

that this error term occurs even for long sample times.

Aperture Time: The delay required between “Hold” command and an input analog transition, so that the

transition does not affect the held output.

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