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MSC1200 Datasheet(PDF) 49 Page - Texas Instruments

Part # MSC1200
Description  Precision Analog -to-Digital Converter
PDF  92 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

MSC1200 Datasheet(HTML) 49 Page - Texas Instruments

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MSC1200
MSC1201
MSC1202
SBAS317E − APRIL 2004 − REVISED MAY 2006
www.ti.com
49
Timer Mode Control (TMOD)
7
6
5
4
3
2
1
0
Reset Value
SFR 89h
TIMER 1
TIMER 0
00h
SFR 89h
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00h
GATE
Timer 1 Gate Control. This bit enables/disables the ability of Timer 1 to increment.
bit 7
0: Timer 1 will clock when TR1 = 1, regardless of the state of pin INT1.
1: Timer 1 will clock only when TR1 = 1 and pin INT1 = 1.
C/T
Timer 1 Counter/Timer Select.
bit 6
0: Timer is incremented by internal clocks.
1: Timer is incremented by pulses on T1 pin when TR1 (TCON.6, SFR 88h) is 1.
M1, M0
Timer 1 Mode Select. These bits select the operating mode of Timer 1.
bits 5−4
M1
M0
MODE
0
0
Mode 0: 8-bit counter with 5-bit prescale.
0
1
Mode 1: 16 bits.
1
0
Mode 2: 8-bit counter with auto reload.
1
1
Mode 3: Timer 1 is halted, but holds its count.
GATE
Timer 0 Gate Control. This bit enables/disables the ability of Timer 0 to increment.
bit 3
0: Timer 0 will clock when TR0 = 1, regardless of the state of pin INT0 (software control).
1: Timer 0 will clock only when TR0 = 1 and pin INT0 = 1 (hardware control).
C/T
Timer 0 Counter/Timer Select.
bit 2
0: Timer is incremented by internal clocks.
1: Timer is incremented by pulses on pin T0 when TR0 (TCON.4, SFR 88h) is 1.
M1, M0
Timer 0 Mode Select. These bits select the operating mode of Timer 0.
bits 1−0
M1
M0
MODE
0
0
Mode 0: 8-bit counter with 5-bit prescale.
0
1
Mode 1: 16 bits.
1
0
Mode 2: 8-bit counter with auto reload.
1
1
Mode 3: Two 8-bit counters.
Timer 0 LSB (TL0)
7
6
5
4
3
2
1
0
Reset Value
SFR 8Ah
TL0.7
TL0.6
TL0.5
TL0.4
TL0.3
TL0.2
TL0.1
TL0.0
00h
TL0.7−0
Timer 0 LSB. This register contains the least significant byte of Timer 0.
bits 7−0
Timer 1 LSB (TL1)
7
6
5
4
3
2
1
0
Reset Value
SFR 8Bh
TL1.7
TL1.6
TL1.5
TL1.4
TL1.3
TL1.2
TL1.1
TL1.0
00h
TL1.7−0
Timer 1 LSB. This register contains the least significant byte of Timer 1.
bits 7−0



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