MSC1200 datasheet(27/92 Pages) TI

27 / 92 page

MSC1200

MSC1201

MSC1202

SBAS317E − APRIL 2004 − REVISED MAY 2006

www.ti.com

POWER ON RESET

The on-chip Power On Reset (POR) circuitry releases the

device from reset when DVDD ≈ 2.0V. The power supply

ramp rate does not affect the POR. If the power supply falls

below 1.0V for longer than 200ms, the POR will execute.

If the power supply falls below 1.0V for less than 200ms,

unexpected operation may occur. If these conditions are

not met, the POR will not execute. For example, a negative

spike on the DVDD supply that does not remain below 1.0V

for at least 200ms, will not initiate a POR.

If the Digital Brownout Reset circuit is on, the POR circuit

has no effect.

DIGITAL BROWNOUT RESET

The Digital Brownout Reset (DBOR) is enabled through

HCR1. If the conditions for proper POR are not met, the

DBOR can be used to ensure proper device operation. The

DBOR will hold the state of the device when the power

supply drops below the threshold level programmed in

HCR1, and then generate a reset when the supply rises

above the threshold level. Note that as the device is

released from reset and program execution begins, the

device current consumption may increase, which can

result in a power supply voltage drop, which may initiate

another brownout condition. Also, the DBOR comparison

is done against an analog reference; therefore, AVDD must

be within its valid operating range for DBOR to function.

The DBOR level should be chosen to match closely with

the application.

That is, with a high external clock

frequency, the DBOR level should match the minimum

operating voltage range for the device or improper

operation may still occur.

ANALOG LOW-VOLTAGE DETECT

The MSC120x contain an analog low-voltage detect

circuit. When the analog supply drops below the value

programmed in LVDCON (SFR E7h), an interrupt is

generated, and/or the flag is set.

IDLE MODE

Idle mode is entered by setting the IDLE bit in the Power

Control register (PCON, 087h). In Idle mode, the CPU,

Timer0, Timer1, and USART are stopped, but all other

peripherals and digital pins remain active. The device can

be returned to active mode via an active internal or external

interrupt. This mode is typically used for reducing power

consumption between ADC samples.

By configuring the device prior to entering Idle mode,

further power reductions can be achieved (while in Idle

mode). These power reductions include powering down

peripherals not in use in the PDCON register (0F1h), and

reducing the system clock frequency by using the System

Clock Divider register (SYSCLK, 0C7h).

STOP MODE

Stop mode is entered by setting the STOP bit in the Power

Control register (PCON, 087h). In Stop mode, all internal

clocks are halted. This mode has the lowest power

consumption. The device can be returned to active mode

only via an external reset or power-on reset (not a

brownout reset).

By configuring the device prior to entering Stop mode,

further power reductions can be achieved (while in Stop

mode). These power reductions include halting the

external clock into the device, configuring all digital I/O

pins as open drain with low output drive, disabling the ADC

buffer, disabling the internal VREF, and setting PDCON to

0FFh to power down all peripherals.

In Stop mode, all digital pins retain their values.

POWER CONSUMPTION CONSIDERATIONS

The

following

suggestions

will

reduce

current

consumption in the MSC120x devices:

Use the lowest supply voltage that will work in the

application for both AVDD and DVDD.

Use the lowest clock frequency that will work in the

application.

Use Idle mode and the system clock divider

whenever possible. Note that the system clock

divider also affects the ADC clock.

Avoid using 8051-compatible I/O mode on the I/O

ports. The internal pull-up resistors will draw current

when the outputs are low.

Use the delay line for Flash Memory control by

setting the FRCM bit in the FMCON register (SFR

EEh).

Power down the internal oscillator in External Clock

mode by setting the PDICLK bit in the PDCON

Power down peripherals when they are not needed.

Refer to SFR PDCON, LVDCON, ADCON0, and

IDAC.

MSC1200 Datasheet(PDF) 27 Page - Texas Instruments

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