OPA690 datasheet(33/45 Pages) TI

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DRIVING CAPACITIVE LOADS

OUTPUT CURRENT AND VOLTAGES

OPA4830

www.ti.com.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008

The second major consideration, touched on in the

To maintain maximum output stage linearity, no

paragraph,

that

the

signal

source

output

short-circuit

protection

provided.

This

impedance becomes part of the noise gain equation

absence of protection is not normally a problem,

and thus influences the bandwidth. For the example

because most applications include a series matching

in Figure 88, the RM value combines in parallel with

resistor at the output that limits the internal power

the

external

Ω

source

impedance

(at

high

dissipation if the output side of this resistor is shorted

frequencies), yielding an effective driving impedance

to ground. However, shorting the output pin directly to

of 50

Ω || 57.6Ω = 26.8Ω. This impedance is added in

the

adjacent

positive

power-supply

(8-pin

series with RG for calculating the noise gain. The

packages), in most cases, destroys the amplifier. If

resulting noise gain is 2.87 for Figure 88, as opposed

additional short-circuit protection is required, consider

to only 2 if RM could be eliminated as discussed

a small series resistor in the power-supply leads. This

above. The bandwidth is therefore lower for the gain

resistor reduces the available output voltage swing

of –2 circuit of Figure 88 (NG = +2.87) than for the

under heavy output loads.

gain of +2 circuit of Figure 72.

The third important consideration in inverting amplifier

design

setting

the

bias

current

cancellation

One of the most demanding and yet very common

resistors

the

noninverting

input

parallel

load conditions for an op amp is capacitive loading.

combination of RT = 750Ω). If this resistor is set equal

Often, the capacitive load is the input of an

to the total dc resistance looking out of the inverting

ADC—including additional external capacitance that

node, the output dc error (as a result of the input bias

may be recommended to improve ADC linearity. A

currents) is reduced to (input offset current) times RF.

high-speed, high open-loop gain amplifier such as the

With the dc blocking capacitor in series with RG, the

OPA4830 can be very susceptible to decreased

dc source impedance looking out of the inverting

stability and closed-loop response peaking when a

mode is simply RF = 750Ω for Figure 88. To reduce

capacitive load is placed directly on the output pin.

the additional high-frequency noise introduced by this

When the primary considerations are frequency

resistor

and

power-supply

feed-through,

RT is

response flatness, pulse response fidelity, and/or

bypassed with a capacitor.

distortion, the simplest and most effective solution is

to isolate the capacitive load from the feedback loop

by inserting a series isolation resistor between the

amplifier output and the capacitive load.

The OPA4830 provides outstanding output voltage

capability.

For

the

+5V

supply,

under

no-load

The Typical Characteristics show the recommended

conditions at +25

°C, the output voltage typically

RS versus capacitive load and the resulting frequency

swings closer than 90mV to either supply rail.

response at the load. Parasitic capacitive loads

greater

than

2pF

can

begin

degrade

the

The minimum specified output voltage and current

performance of the OPA4830. Long PCB traces,

specifications over temperature are set by worst-case

unmatched cables, and connections to multiple

simulations at the cold temperature extreme. Only at

devices

can

easily

exceed

this

value.

Always

cold startup does the output current and voltage

consider

this

effect

carefully,

and

add

the

decrease to the numbers shown in the specification

recommended series resistor as close as possible to

tables. As the output transistors deliver power, the

the output pin (see the Board Layout Guidelines

junction temperatures increase, decreasing the VBEs

section).

(increasing the available output voltage swing), and

increasing the current gains (increasing the available

The criterion for setting this RS resistor is a maximum

output

current).

steady-state

operation,

the

bandwidth, flat frequency response at the load. For a

available output voltage and current is always greater

gain of +2, the frequency response at the output pin

than

that

shown

the

over-temperature

is already slightly peaked without the capacitive load,

specifications, because the output stage junction

requiring relatively high values of RS to flatten the

temperatures are higher than the minimum specified

response at the load. Increasing the noise gain also

operating ambient temperature.

reduces the peaking (see Figure 78).

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