CS43L43 datasheet(30/36 Pages) CIRRUS

30 / 36 page

CS43L43

DS479PP3

SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE (Inputs: Logic “0” =

GND, Logic “1” = VL.)

Notes: 5. This serial clock is required only in Control Port Mode when the MCLK Divide bit is enabled.

Parameters

Symbol

Min

Max

Units

External SCLK Mode

MCLK Frequency

1.024

51.2

MHz

MCLK Duty Cycle

Input Sample Rate

Single-Speed Mode

Double-Speed Mode

100

kHz

LRCK Duty Cycle

SCLK Pulse Width Low

tsclkl

SCLK Pulse Width High

tsclkh

SCLK Period

tsclkw

-s

SCLK Frequency

(Note 10)

SCLK rising to LRCK edge delay

tslrd

SCLK rising to LRCK edge setup time

tslrs

SDATA valid to SCLK rising setup time

tsdlrs

SCLK rising to SDATA hold time

tsdh

MCLK

------------------

MCLK

------------------

MCLK

------------------

sclkh

slrs

slrd

sdlrs

sd h

sclkl

SD AT A

SC LK

LR C K

Figure 19. External Se-

rial Mode Input Timing

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