CS4812 datasheet(17/36 Pages) CIRRUS

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CS4812

DS291PP3

3. FUNCTIONAL DESCRIPTION

3.1

Overview

The CS4812 is a complete audio subsystem on a

chip, integrating an DSP with on-chip RAM, two

24-bit ADCs, two 24-bit DACs, and a serial control

port.

The sigma-delta ADCs include linear phase digital

anti-aliasing filters and only require a single-pole

external passive filter.

The sigma-delta DACs include analog switched-

capacitor anti-image filters and require an external

second or third order active filter that can be easily

integrated into an output differential-to-single-end-

ed converter circuit.

The serial control port is designed to accommodate

I2C® or SPI interfaces and can operate in master or

slave mode. It allows interfacing to external non-

volatile memory for stand-alone operation or to a

host-controller for real-time control. All communi-

cations between the DSP and an external EEPROM

or host-controller are handled through the serial

control port.

3.2

Analog Inputs

3.2.1

Line Level Inputs

AINR+, AINR-, AINL+, and AINL- are the line

level analog inputs (See Figure 5). These pins are

internally biased to the CMOUT voltage of 2.3 V.

A DC blocking capacitor placed in series with the

input pins allows signals centered around 0 V to be

input to the CS4812. Figure 5 shows operation with

a single-ended input source. This source may be

supplied to either the positive or negative input as

long as the unused input is connected to ground

through capacitors as shown. When operated with

single-ended inputs, distortion will increase at in-

put levels higher than -1 dBFS. If better perfor-

mance is required, a single-ended-to-differential

converter, shown in Figure 10, may be used. It pro-

vides unity gain, DC blocking and anti-alias filter-

ing.

Inputs may be externally AC or DC coupled. This

permits use of the ADCs for input of audio signals

or for measurement of DC control voltages. By de-

fault, an internal high pass filter removes any DC

offsets from both of the ADC inputs. If measure-

ment of DC is required on either of the ADC inputs,

then the on-chip high pass filter must be disabled.

Analog audio input signals that are DC coupled

must be biased at 2.3 V to maintain proper input

10 k

4.7 k

AIN -

µF

AIN +

2.2 nf

150

10 k

input signal

(2 Vrms max)

+5 V

CMOUT

0.1

µF

10 µf

GND

Figure 10. Recommended Line Input Buffer

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