DS1075-80 datasheet(7/18 Pages) DALLAS

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DS1075

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Figure 5

Figure 6

SELECT TIMING

If the PDN bit is set to “0”, the PDN / SELX pin can be used to switch between the internal oscillator and

an externalor crystal reference. The “Enabling Sequencer” is again employed to ensure this transition

occurs in a glitch-free fashion. Two asynchronous clock signals are involved, INTCLK is the internal

reference oscillator divided by one or whatever value of M is selected. EXTCLK is the clock signal fed

into the OSCIN pin, or the clock resulting from a crystal connected between OSCIN and XTAL. The

behavior of OUT0 is described in the following paragraphs, the OUT pin will behavior similarly but will

be divided by N.

FROM INTERNAL TO EXTERNAL CLOCK

This is accomplished by a high to low transition on the SELX pin. This transaction is detected on the

falling edge of INTCLK. The output OUT0 will be held low for a minimum of half the period of

INTCLK (tI/2), then if EXTCLK is low it will be routed through to OUT0. If EXTCLK is high the

switching will not occur until EXTCLK returns to a low level.

DS1075-80 Datasheet(PDF) 7 Page - Dallas Semiconductor