ICS810251I Data Sheet

VCXO AND SYNCHRONOUS ETHERNET JITTER ATTENUATOR

ICS810251AGI REVISION B OCTOBER 5, 2012

5

©2012 Integrated Device Technology, Inc.

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has

been reached under these conditions.

NOTE: Characterized using a 616Hz bandwidth filter.

NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 2: Please refer to the Phase Noise Plot.

NOTE 3: Specified with the VCXO-PLL free running high.

NOTE 4: Specified with the VCXO-PLL locked.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Reference Frequency

25

MHz

125

MHz

VCXO-PLL Frequency

25

MHz

Output Frequency

25

MHz

Cycle-to-Cycle Jitter; NOTE 1

35

ps

tjit

RMS Phase Jitter (Random);

NOTE 2

1kHz – 1MHz

0.24

ps

Period jitter

10

ps

Output Rise/Fall Time

20% to 80%

700

2200

ps

odc

Output Duty Cycle; NOTE 3

48

52

%

odc

Output Duty Cycle; NOTE 4

44

56

%