ICS810251 datasheet(7/15 Pages) IDT

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ICS810251I Data Sheet

VCXO AND SYNCHRONOUS ETHERNET JITTER ATTENUATOR

ICS810251AGI REVISION B OCTOBER 5, 2012

Parameter Measurement Information

3.3V Core/3.3V LVCMOS Output Load AC Test Circuit

Cycle-to-Cycle Jitter

Period Jitter

2.5V Core/2.5V LVCMOS Output Load AC Test Circuit

RMS Phase Jitter

Output Rise/Fall Time

SCOPE

GND

VDD,

1.65V¬±5

-1.65V¬±5

VDDO

VDDA

1.65V¬±5

➤

DDO

tcycle n

tcycle n+1

tjit(cc) =

|tcycle n – tcycle n+1|

1000 Cycles

VOH

VREF

VOL

Mean Period

(First edge after trigger)

Reference Point

(Trigger Edge)

σ contains 68.26% of all measurements

σ contains 95.4% of all measurements

σ contains 99.73% of all measurements

σ contains 99.99366% of all measurements

σ contains (100-1.973x10-7)% of all measurements

Histogram

SCOPE

GND

VDD,

1.25V¬±5

-1.25V¬±5

VDDO

1.25V¬±5

VDDA

Phase Noise Mask

Offset Frequency

Phase Noise Plot

RMS Jitter = Area Under the Masked Phase Noise Plot

20%

80%

20%

t F

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