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3.0 DMA FUNCTIONALITY

Figure 2 shows a block diagram representing the structure

of the DMA controller. This figure also shows how the DMA

interfaces with the rest of the system.

Each DMA channel has 6 possible modes that it can

operate in. These are as follows:

3.1 IDLE MODE

The channel goes into IDLE mode after an active hardware

reset or after resetting the status flags. When in IDLE mode,

the channel goes into PEND_CHAIN mode when activated by

writing the Mode register. No parity check is done on this

3.2 PEND_CHAIN MODE

Once the channel has been activated, it goes from IDLE to

PEND_CHAIN mode. In this mode, the first instruction is read

(all 8 words). If a parity error is detected, the channel goes to

the ERROR mode. If the read is successful, the channel will

stay in the PEND_CHAIN mode until either an active request is

received or the Channel Request Pending bit is set in the

Channel Status Register. At this time, the channel progresses

to the PEND_REQ mode.

3.3 PEND_REQ MODE

In this mode, the Mode / Link word is checked to make sure

it doesn’t de-activate the channel (sending the device back to

IDLE mode). If the channel remains active, the device sits in

PEND_REQ mode until the system bus arbiter grants the DMA

bus control. Once this occurs, the transfer commences and the

DMA enters TRANSFER mode.

3.4 TRANSFER MODE

If at any time during the transfer an error occurs, the

channel is set into ERROR mode. If the transfers are clean of

errors, then the behaviour of the device is dependant on the

type of transfer mode that was programmed by the currently

executing instruction.

3.4.1 Single/Double Word and External Area to Area Mode

Within these modes, the DMA executes each data transfer

seperately, ie. between each single / double word transfer, the

request is removed. The DMA goes back into PEND_REQ

mode after each transfer and waits for the next request to be

granted.

3.4.2 Burst Area to Area Mode

With this type of transfer, the DMA transfers data whilst the

bus control is granted. The channel request signal remains

active. When control is removed by the arbiter, the device sits

in the PEND_TRANS mode until re-granted. If the burst mode

is area to area with interval timing, then between each transfer,

the channel has to count the interval.

Once a transfer has completed, the channel either sets the

EOT bit and sits waiting for this to be reset before it goes back

into INIT mode, or the instruction is chained and the channel

jumps back to the PEND_CHAIN mode where it can read the

next instruction details for the next transfer. If during any

transfer mode, the channel is de-activated, the channel goes

back to INIT mode. If at any time, an error is detected, the

device goes into ERROR mode.

3.5 ERROR MODE

This mode is entered from the PEND_CHAIN mode if a

parity error is detected during the instruction register reads.

The error mode can also be entered from theTRANSFER

mode. This can happen if PEN, MPROEN or EXADEN are

activated by trying to access one of the data transfer addreses.

An interrupt is generated in this mode. The only way to leave

this mode is to reset all the error flags.

3.6 WORD TRANSFER MODES

It is possible to run each channel in single, double, and

burst mode transfers.

3.6.1 Single Word Transfer

In single word transfer mode, the generation of each

request on a channel causes the DMA controller to issue an

external request that lasts for one bus cycle. The request is de-

activated before the end of the bus cycle to allow other users to

aquire bus control. If the transfer is to or from a device needing

longer than one machine cycle (2 CLK cycles) then the cycle

can be extended using handshaking of the DMA request and

acknowledge lines.

3.6.2 Double Word Transfer

In double word mode, each request on a channel causes

the DMA controller to request bus control for 2 machine cycles

to allow the transfer of 2 16-bit data words. The data is

transferred to consecutive addresses and the bus is locked

between each word transfer to protect the transfer. The most

significant word to be transferred has the lowest address and

is transferred first (following the 1750 standard). The request is

de-activated before the end of the second bus cycle to allow

other bus users to take control. If an extended cycle is needed,

the handshaking mechanism doesn’t word in this mode and

the RDYN signal must be kept high for as long as required.

3.6.3 Burst Mode

In burst mode, one request to the channel causes the DMA

to request bus control for a complete block of data to be

transferred. The DMA de-asserts the request line on the last

transfer cycle to allow other users to take bus control.

Consequently, if the transfers are chained together, the CPU

may be able to get bus control between 2 blocks of data

transfer. If extended bus cycles are needed, the RDYN

mechanism can be used (handshaking does not work in this

mode).

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