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3.10 SOFTWARE PROGRAMMING

DMA requests can be generated in software by writing the

CRQP bit in the Channel Status register. If the channel is

active, the DMA will then request bus control. If the DREQN

signal on that channel is not active, the DMA finishes the cycle

as soon as the memory is ready. There is no handshaking with

the IO port. DACKN is deasserted when the memory is ready.

If DREQN is asserted but is masked, the handshaking is active

and operates normally.

Interrupts can be generated in software by setting either a

channel EOT flag or any error flag. This can only be done

when the DMA is in PEND_CHAIN mode. If an error flag is set,

the device goes straight to ERROR mode. If the EOT flag is

set, the device looks as if it has completed the transfer. It will

then just sit and wait for the EOT flag to be cleared before

entering IDLE mode. If both flags are set simultaneously, the

device remains in PEND_CHAIN mode. Setting an error flag

when EOT is set resets EOT and the device goes to ERROR

mode. Setting EOT when an error flag is set clears the error

and the DMA sits in the finish transfer mode.

3.11 CASCADING DMA CONTROLLERS

DMA controllers are cascaded in series. For each DMA

added, an extra 4 channels become available. To cascade the

devices, the strobes, control signals and address and data

busses are connected in parallel. Of the bus arbitration

signals, LOCKN and GRANTN should be connected in parallel

and REQINN, GEINN and GEOUTN shoudl be daisy-chained.

INTRN and PEN can either be ORed together with external

glue logic or input to seperate CPU interrupts. Figure 3 shows

the cascade connections.

Figure 3: Cascading DMA Controllers

Bus

Arbiter

DMAC 1

DMAC 2

REQN

REQINN

GEOUTN

GEINN

GRANTN

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